JAJSI35D July 2003 – August 2020 SN74LVC1G126-Q1
PRODUCTION DATA
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The SN74LVC1G126-Q1 device contains a dual buffer gate with output enable control and performs the Boolean function Y = A.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.