JAJSHV8L
July 2002 – August 2019
SN74LVC1G18
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
概略回路図
4
改訂履歴
5
Pin Configuration and Functions
Pin Functions
5.1
Logic Diagram (Positive Logic)
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics, –40 to 85°C
6.7
Switching Characteristics, –40 to 125°C
6.8
Operating Characteristics
6.9
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Balanced CMOS 3-State Outputs
8.3.2
Partial Power Down (Ioff)
8.3.3
Standard CMOS Inputs
8.3.4
Over-voltage Tolerant Inputs
8.3.5
Clamp Diode Structure
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.1.1
Power Considerations
9.2.1.2
Input Considerations
9.2.1.3
Output Considerations
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
デバイスおよびドキュメントのサポート
12.1
ドキュメントのサポート
12.1.1
関連資料
12.2
ドキュメントの更新通知を受け取る方法
12.3
コミュニティ・リソース
12.4
商標
12.5
静電気放電に関する注意事項
12.6
Glossary
13
メカニカル、パッケージ、および注文情報
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
DBV|6
DSF|6
YZP|6
DCK|6
DRY|6
サーマルパッド・メカニカル・データ
DRY|6
QFND138E
発注情報
jajshv8l_oa
jajshv8l_pm
9.2.1
Design Requirements
Each analog switch must be controlled by the system controller, but only when the other switch is disabled.
When the input S is low, the Y
0
output is selected and the Y
1
output is in the high impedance state
When the input S is high, the Y
1
output is selected and the Y
0
output is in the high impedance state
When the input A is high, the selected analog switch must be closed
When the input A is low, the selected analog switch must be open