SCES414P November   2002  – November 2016 SN74LVC1G57

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Schmitt-Trigger Inputs
      2. 8.3.2 Inputs Accept Voltages to 5.5 V
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Application Truth Table
        2. 9.2.1.2 Schmitt-Trigger Inputs
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
    • Supports Down Translation to VCC
  • Max tpd of 6.3 ns at 3.3 V
  • Schmitt-Triggered Inputs
  • Low Power Consumption, 10-µA Maximum ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Available in the Texas Instruments
    NanoFree™ Package

2 Applications

  • Active Noise Cancellation (ANC)
  • Barcode Scanners
  • Blood Pressure Monitors
  • CPAP Machines
  • Cable Solutions
  • Embedded PCs
  • Field Transmitter: Temperature or Pressure Sensors
  • HVAC: Heating, Ventilating, and Air Conditioning
  • TVs: High-Definition (HDTV), LCD, and Digital
  • Video Communications Systems

3 Description

The SN74LVC1G57 device features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter, and buffer. All inputs can be connected to VCC or GND.

This device functions as an independent gate, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

This configurable multiple-function gate is designed for 1.65-V to 5.5-V VCC operation.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

Device Information(1)

DEVICE NAME PACKAGE BODY SIZE (NOM)
SN74LVC1G57DBV SOT-23 (6) 2.90 mm × 1.60 mm
SN74LVC1G57DCK SC70 (6) 2.00 mm × 1.25 mm
SN74LVC1G57DRL SOT (6) 1.60 mm × 1.20 mm
SN74LVC1G57DRY SON (6) 1.45 mm × 1.00 mm
SN74LVC1G57DSF SON (6) 1.00 mm × 1.00 mm
SN74LVC1G57YZP DSBGA (6) 1.41 mm × 0.91 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram (Positive Logic)

SN74LVC1G57 ld_ces414.gif