SCES222Q April   1999  – June 2017 SN74LVC1G86

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics, CL = 15 pF
    7. 6.7 Switching Characteristics, CL = 30 pF or 50 pF
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
      2. 8.3.2 Standard CMOS Inputs
      3. 8.3.3 Clamp Diodes
      4. 8.3.4 Partial Power Down (Ioff)
      5. 8.3.5 Over-voltage Tolerant Inputs
    4. 8.4 Function Table
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DBV|5
  • DCK|5
  • DRL|5
  • YZP|5
サーマルパッド・メカニカル・データ
発注情報

8 Detailed Description

8.1 Overview

The SN74LVC1G86 device performs the Boolean function Y = AB + AB in positive logic. This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.

A common application is as a true and complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

8.2 Functional Block Diagram

SN74LVC1G86 ces222_ls.gif
These are five equivalent exclusive-OR symbols valid for an SN74LVC1G86 gate in positive logic; negation may be shown at any two ports.

8.3 Feature Description

8.3.1 Balanced High-Drive CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The high drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings must be followed at all times.

8.3.2 Standard CMOS Inputs

Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage, given in the Recommended Operating Conditions, and the maximum input leakage current, given in the Electrical Characteristics, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating Conditions to avoid excessive currents and oscillations. If tolerance to a slow or noisy input signal is required, a device with a Schmitt-trigger input should be utilized to condition the input signal prior to the standard CMOS input.

8.3.3 Clamp Diodes

The inputs and outputs to this device have negative clamping diodes.

CAUTION

Avoid any voltage below or above the input or output voltage specified in the Absolute Maximum Ratings. In this event, the current must be limited to the maximum input or output clamp current value indicated in the Absolute Maximum Ratings to avoid damage to the device.
SN74LVC1G86 SN74LVC1G79-ClampDiodes.gif Figure 3. Electrical Placement of Clamping Diodes for Each Input and Output

8.3.4 Partial Power Down (Ioff)

The inputs and outputs for this device enter a high impedance state when the supply voltage is 0 V. The maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical Characteristics.

8.3.5 Over-voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage so long as they remain below the maximum input voltage value specified in the Recommended Operating Conditions.

8.4 Function Table

Table 1 lists the functional modes of the SN74LVC1G86 device.

Table 1. Function Table

INPUTS OUTPUT
Y
A B
L L L
L H H
H L H
H H L