The SN74LVC1G97 device features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All inputs can be connected to VCC or GND.
This configurable multiple-function gate is designed for 1.65-V to 5.5-V VCC operation.
This device functions as an independent gate, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.
NanoFree package technology is a major break-through in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
SN74LVC1G97DBV | SOT-23 (6) | 2.90 mm × 1.60 mm |
SN74LVC1G97DCK | SC70 (6) | 2.00 mm × 1.25 mm |
SN74LVC1G97DRL | SOT (6) | 1.60 mm × 1.20 mm |
SN74LVC1G97DRY | 1.45 mm × 1.00 mm | |
SN74LVC1G97DSF | 1.00 mm × 1.00 mm | |
SN74LVC1G97YZP | DSBGA (6) | 1.41 mm × 0.91 mm |
Changes from M Revision (June 2015) to N Revision
Changes from L Revision (December 2013) to M Revision
Changes from K Revision (October 2011) to L Revision
PIN | I/O | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | DCT, DCU, DRY | YZP | |||
In0 | 3 | C1 | I | Input 0 | |
In1 | 1 | A1 | I | Input 1 | |
In2 | 6 | A2 | I | Input 2 | |
GND | 2 | B1 | — | Ground | |
VCC | 5 | B2 | — | Power | |
Y | 4 | C2 | O | Output |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VCC | Supply voltage | –0.5 | 6.5 | V | |
VI | Input voltage(2) | –0.5 | 6.5 | V | |
VO | Voltage applied to any output in the high-impedance or power-off state(2) | –0.5 | 6.5 | V | |
VO | Voltage applied to any output in the high or low state(2)(3) | –0.5 | VCC + 0.5 | V | |
IIK | Input clamp current | VI < 0 V | –50 | mA | |
IOK | Output clamp current | VO < 0 V | –50 | mA | |
IO | Continuous output current | ±50 | mA | ||
Continuous current through VCC or GND | ±100 | mA | |||
TJ | Junction temperature | 150 | °C | ||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101\(2) | ±1000 |
THERMAL METRIC(1) | SN74LVC1G97 | UNIT | ||||
---|---|---|---|---|---|---|
DBV (SOT-23) | DCK (SC70) | DRL (SOT) | YZP (DSBGA) | |||
6 PINS | 6 PINS | 6 PINS | 6 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 165 | 259 | 142 | 123 | °C/W |
PARAMETER | TEST CONDITIONS | VCC | –40°C TO +85°C | –40°C TO +125°C | UNIT | ||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP(1) | MAX | MIN | TYP(1) | MAX | ||||
VT+
Positive-going input threshold voltage |
1.65 V | 0.79 | 1.16 | 0.79 | 1.16 | V | |||
2.3 V | 1.11 | 1.56 | 1.11 | 1.56 | |||||
3 V | 1.5 | 1.87 | 1.5 | 1.87 | |||||
4.5 V | 2.16 | 2.74 | 2.16 | 2.74 | |||||
5.5 V | 2.61 | 3.33 | 2.61 | 3.33 | |||||
VT–
Negative-going input threshold voltage |
1.65 V | 0.35 | 0.62 | 0.35 | 0.62 | V | |||
2.3 V | 0.58 | 0.87 | 0.58 | 0.87 | |||||
3 V | 0.84 | 1.19 | 0.84 | 1.19 | |||||
4.5 V | 1.41 | 1.9 | 1.41 | 1.9 | |||||
5.5 V | 1.87 | 2.29 | 1.87 | 2.29 | |||||
ΔVT
Hysteresis (VT+ – VT–) |
1.65 V | 0.3 | 0.62 | 0.3 | 0.62 | V | |||
2.3 V | 0.4 | 0.8 | 0.4 | 0.8 | |||||
3 V | 0.53 | 0.87 | 0.53 | 0.87 | |||||
4.5 V | 0.71 | 1.04 | 0.71 | 1.04 | |||||
5.5 V | 0.71 | 1.11 | 0.71 | 1.11 | |||||
VOH | IOH = –100 µA | 1.65 V to 5.5 V | VCC – 0.1 | VCC – 0.1 | V | ||||
IOH = –4 mA | 1.65 V | 1.2 | 1.2 | ||||||
IOH = –8 mA | 2.3 V | 1.9 | 1.9 | ||||||
IOH = –16 mA | 3 V | 2.4 | 2.4 | ||||||
IOH = –24 mA | 2.3 | 2.3 | |||||||
IOH = –32 mA | 4.5 V | 3.8 | 3.8 | ||||||
VOL | IOL = 100 µA | 1.65 V to 5.5 V | 0.1 | 0.1 | V | ||||
IOL = 4 mA | 1.65 V | 0.45 | 0.45 | ||||||
IOL = 8 mA | 2.3 V | 0.3 | 0.3 | ||||||
IOL = 16 mA | 3 V | 0.4 | 0.45 | ||||||
IOL = 24 mA | 0.55 | 0.55 | |||||||
IOL = 32 mA | 4.5 V | 0.55 | 0.58 | ||||||
II | VI = 5.5 V or GND | 0 to 5.5 V | ±5 | ±5 | µA | ||||
Ioff | VI or VO = 5.5 V | 0 | ±10 | ±10 | µA | ||||
ICC | VI = 5.5 V or GND, IO = 0 | 1.65 V to 5.5 V | 10 | 10 | µA | ||||
ΔICC | One input at VCC – 0.6 V, Other inputs at VCC or GND |
3 V to 5.5 V | 500 | 500 | µA | ||||
CI | VI = VCC or GND | 3.3 V | 3.5 | 3.5 | pF |
PARAMETER | FROM (INPUT) |
TO (OUTPUT) |
–40°C TO 85°C | UNIT | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|
VCC = 1.8 V ± 0.15 V |
VCC = 2.5 V ± 0.2 V |
VCC = 3.3 V ± 0.3 V |
VCC = 5 V ± 0.5 V |
||||||||
MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX | ||||
tpd | Any In | Y | 3.2 | 14.4 | 2 | 8.3 | 1.5 | 6.3 | 1.1 | 5.1 | ns |
PARAMETER | FROM (INPUT) |
TO (OUTPUT) |
–40°C TO 125°C | UNIT | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|
VCC = 1.8 V ± 0.15 V |
VCC = 2.5 V ± 0.2 V |
VCC = 3.3 V ± 0.3 V |
VCC = 5 V ± 0.5 V |
||||||||
MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX | ||||
tpd | Any In | Y | 3.2 | 16.4 | 2 | 9.3 | 1.5 | 7.3 | 1.1 | 6.1 | ns |
PARAMETER | TEST CONDITIONS |
VCC = 1.8 V | VCC = 2.5 V | VCC = 3.3 V | VCC = 5 V | UNIT | |
---|---|---|---|---|---|---|---|
TYP | TYP | TYP | TYP | ||||
Cpd | Power dissipation capacitance | f = 10 MHz | 22 | 23 | 23 | 26 | pF |
This configurable multiple-function gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G97 device features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose variations of common logic functions, like AND, OR, and NOT. All inputs can be connected to VCC or GND.
This device functions as an independent gate, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.
This device is fully-specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The SN74LVC1G97 device has a wide operating VCC range of 1.65 V to 5.5 V, which allows use in a broad range of systems. The 5.5-V I/Os allow down translation and also allow voltages at the inputs when VCC = 0 V.
Table 1 shows the functional modes of SN74LVC1G97.
INPUTS | OUTPUT | ||
---|---|---|---|
In2 | In1 | In0 | Y |
L | L | L | L |
L | L | H | L |
L | H | L | H |
L | H | H | H |
H | L | L | L |
H | L | H | H |
H | H | L | L |
H | H | H | H |
LOGIC FUNCTION | FIGURE NUMBER |
---|---|
2-to-1 data selector | Figure 3 |
2-input AND gate | Figure 4 |
2-input OR gate with one inverted input | Figure 5 |
2-input NAND gate with one inverted input | Figure 5 |
2-input AND gate with one inverted input | Figure 6 |
2-input NOR gate with one inverted input | Figure 6 |
2-input OR gate | Figure 7 |
Inverter | Figure 8 |
Noninverted buffer | Figure 9 |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Validate and test the design implementation to confirm system functionality.
The SN74LVC1G97 device offers flexible configuration for many design applications. This example describes basic power sequencing using the AND gate configuration. Power sequencing is often used in applications that require a processor or other delicate device with specific voltage timing requirements in order to protect the device from malfunctioning.
The SN74LVC1G97 device uses CMOS technology and has balanced output drive. Avoid bus contentions that can drive currents that can exceed maximum limits.
The SN74LVC1G97 allows for performing logical Boolean functions with digital signals. Maintain input signals as close as possible to either 0 V or VCC for optimal operation.
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the Recommended Operating Conditions table.
To prevent power disturbance, ensure good bypass capacitance for each VCC terminal. For devices with a single-supply, a 0.1-μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μF capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dual supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors with values of 0.1 μF and 1 μF are commonly used in parallel. Place the bypass capacitor as close to the power terminal as possible for best results.
When using multiple-bit logic devices, inputs must never float.
In many cases, functions (or parts of functions) of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or when only 3 of the 4 buffer gates are used. Such input pins must not be left unconnected, because the undefined voltages at the outside connections result in undefined operational states. Figure 13 specifies the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally they are tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs, unless the part is a transceiver. If the transceiver has an output enable pin, it disables the output section of the part when asserted, which does not disable the input section of the I/Os. Therefore, the I/Os cannot float when disabled.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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