SCES416N December   2002  – January 2017 SN74LVC1G97

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Validate and test the design implementation to confirm system functionality.

9.1 Application Information

The SN74LVC1G97 device offers flexible configuration for many design applications. This example describes basic power sequencing using the AND gate configuration. Power sequencing is often used in applications that require a processor or other delicate device with specific voltage timing requirements in order to protect the device from malfunctioning.

SN74LVC1G97 simp_app_sces416.gif Figure 10. Simplified Application

9.2 Typical Application

SN74LVC1G97 typ_app_sces416.gif Figure 11. Typical Application

9.2.1 Design Requirements

  • Recommended input conditions:
  • Recommended output conditions:
    • Load currents must not exceed ±50 mA.
  • Frequency selection criterion:
    • Figure 12 illustrates the effects of frequency on output current.
    • Added trace resistance and capacitance can reduce maximum frequency capability. Follow the layout practices listed in the Layout section.

9.2.2 Detailed Design Procedure

The SN74LVC1G97 device uses CMOS technology and has balanced output drive. Avoid bus contentions that can drive currents that can exceed maximum limits.

The SN74LVC1G97 allows for performing logical Boolean functions with digital signals. Maintain input signals as close as possible to either 0 V or VCC for optimal operation.

9.2.3 Application Curve

SN74LVC1G97 sces416_appcurve1.png Figure 12. Simulated Input-to-Output Voltage Response Showing Propagation Delay at VCC = 5 V