JAJSKB1N
December 2003 – June 2024
SN74LVC1T45
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics (VCCA = 1.8V ± 0.15V)
5.7
Switching Characteristics (VCCA = 2.5V ± 0.2V)
5.8
Switching Characteristics (VCCA = 3.3V ± 0.3V)
5.9
Switching Characteristics (VCCA = 5V ±0.5V)
5.10
Operating Characteristics
5.11
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65V to 5.5V Power-Supply Range
7.3.2
Support High Speed Translation
7.3.3
Ioff Supports Partial Power-Down Mode Operation
7.3.4
Balanced High-Drive CMOS Push-Pull Outputs
7.3.5
Glitch-Free Power Supply Sequencing
7.3.6
Vcc Isolation
7.4
Device Functional Modes
8
Applications and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Unidirectional Logic Level-Shifting Application
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Curve
8.2.2
Bidirectional Logic Level-Shifting Application
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.2.1
Enable Times
8.2.2.3
Application Curve
42
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
ドキュメントの更新通知を受け取る方法
9.3
サポート・リソース
9.4
Trademarks
9.5
静電気放電に関する注意事項
9.6
用語集
10
Revision History
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
YZP|6
MXBG347
DPK|6
MPSS055A
DCK|6
MPDS114D
DRL|6
MPDS159H
DBV|6
MPDS026P
サーマルパッド・メカニカル・データ
8.2.1.3
Application Curve
Figure 8-2
Translation Up (1.8V to 5V) at 2.5 MHz