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This dual 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G00 device performs the Boolean function Y = A × B or Y = A + B in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
SN74LVC2G00 | SM8 (8) | 2.95 mm × 2.80 mm |
US8 (8) | 2.30 mm × 2.00 mm | |
DSBGA (8) | 1.91 mm × 0.91 mm |
Changes from M Revision (November 2013) to N Revision
Changes from L Revision (January 2007) to M Revision
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | DCT, DCU, YZP | ||
1A | 1 | I | A input for gate 1 |
1B | 2 | I | B input for gate 1 |
2Y | 3 | O | Output for gate 2 |
GND | 4 | — | Ground |
2A | 5 | I | A input for gate 2 |
2B | 6 | I | B input for gate 2 |
1Y | 7 | O | Output for gate 1 |
VCC | 8 | I | Power input. |