JAJSU83 April 2024 SN74LVC2G100
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CLR1 | 1 | I | Clear for Channel 1, active low |
DA1 | 2 | I | Channel 1, Input A |
DB1 | 3 | I | Channel 1, Input B |
DC1 | 4 | I | Channel 1, Input C |
DD1 | 5 | I | Channel 1, Input D |
Q1 | 6 | O | Channel 1, Output Q |
CLK1 | 7 | I | Clock for Channel 1, rising edge triggered |
GND | 8 | G | Ground |
CLK2 | 9 | I | Clock for Channel 2, rising edge triggered |
Q2 | 10 | O | Channel 2, Output Q |
DD2 | 11 | I | Channel 2, Input D |
DC2 | 12 | I | Channel 2, Input C |
DB2 | 13 | I | Channel 2, Input B |
DA2 | 14 | I | Channel 2, Input A |
CLR2 | 15 | I | Clear for Channel 2, active low |
VCC | 16 | P | Positive Supply |
Thermal Pad(2) | — | The thermal pad can be connected to GND or left floating. Do not connect to any other signal or supply. |