SN74LVC2G32 Dual 2-Input Positive-OR Gate

1 Features

• Available in the Texas Instruments
  NanoFree™ Package
• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Maximum t_pd of 3.8 ns at 3.3 V
• Low Power Consumption, 10-µA Maximum I_CC
• ±24-mA Output Drive at 3.3 V
• Typical V_OLP (Output Ground Bounce)
  <0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
  >2 V at V_CC = 3.3 V, T_A = 25°C
• I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
• Can Be Used as a Down Translator to Translate Inputs From a Maximum of 5.5 V Down to the V_CC Level
• Latch-Up Performance Exceeds 100 mA Per
  JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human Body Model (A114-A)
  • 1000-V Charged-Device Model (C101)

2 Applications

• Down Translation
• Logical OR

3 Description

This dual 2-input positive-OR gate is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC2G32 device performs the Boolean function in positive logic.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

1. For all available packages, see the orderable addendum at the end of the data sheet.

4 Revision History

Changes from M Revision (November 2013) to N Revision

• Added Applications section, Device Information table, Pin Configuration and Functions section, ESD Ratings table, Thermal Information table, Typical Characteristics section, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from L Revision (February 2007) to M Revision

• Updated document to new TI data sheet format.Go
• Removed Ordering Information table.Go
• Updated Features.Go
• Updated operating temperature range.Go

5 Pin Configuration and Functions

DCT Package

8-Pin SSOP

Top View

DCU Package

8-Pin VSSOP

Top View

YZP Package

8-Pin DSBGA

Bottom View

See mechanical drawing for dimensions