SCES635B JULY 2005 – April 2015 SN74LVCH16T245
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The SN74LVCH16T245 device can be used in level-shifting applications for interfacing devices and addressing mixed voltage incompatibility. The SN74LVCH16T245 device is ideal for data transmission where direction is different for each channel.
Calculate the enable times for the SN74LVCH16T245 using the following formulas:
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the SN74LVCH16T245 initially is transmitting from A to B, then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay.
This device uses drivers which are enabled depending on the state of the DIR pin. The designer must know the intended flow of data and take care not to violate any of the high or low logic levels. It is important that unused data inputs not be floating, as this can cause excessive internal leakage on the input CMOS structure. Make sure to tie any unused input and output ports directly to ground. For this design example, use the parameters listed in Table 2.
DESIGN PARAMETERS | EXAMPLE VALUE | |||
---|---|---|---|---|
Input voltage range | 1.65 V to 5.5 V | |||
Output voltage | 1.65 V to 5.5 V |
To begin the design process, determine the following: