JAJSLQ8A September   2021  – December 2021 SN74LXC1T45

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics, VCCA = 1.2 ± 0.1 V
    7. 6.7  Switching Characteristics, VCCA = 1.5 ± 0.1 V
    8. 6.8  Switching Characteristics, VCCA = 1.8 ± 0.15 V
    9. 6.9  Switching Characteristics, VCCA = 2.5 ± 0.2 V
    10. 6.10 Switching Characteristics, VCCA = 3.3 ± 0.3 V
    11. 6.11 Switching Characteristics, VCCA = 5.0 ± 0.5 V
    12. 6.12 スイッチング特性：Tsk、TMAX
    13. 6.13 Operating Characteristics
    14. 6.14 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Load Circuit and Voltage Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CMOS Schmitt-Trigger Inputs with Integrated Pulldowns
        1. 8.3.1.1 I/O's with Integrated Dynamic Pull-Down Resistors
        2. 8.3.1.2 Control Inputs with Integrated Static Pull-Down Resistors
      2. 8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
      3. 8.3.3 Partial Power Down (Ioff)
      4. 8.3.4 VCC Isolation and VCC Disconnect (Ioff-float)
      5. 8.3.5 Over-Voltage Tolerant Inputs
      6. 8.3.6 Glitch-Free Power Supply Sequencing
      7. 8.3.7 Negative Clamping Diodes
      8. 8.3.8 Fully Configurable Dual-Rail Design
      9. 8.3.9 Supports High-Speed Translation
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Enable Times
    3. 9.3 Typical Application
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Regulatory Requirements
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

  • f = 1 MHz
  • ZO = 50 Ω
  • Δt/ΔV ≤ 1 ns/V

GUID-0EDCE25A-A2FC-4C7E-9B72-04A128BD6663-low.gif
CL includes probe and jig capacitance.
Figure 7-1 Load Circuit
Table 7-1 Load Circuit Conditions
ParameterVCCORLCLS1VTP
tpdPropagation (delay) time1.1 V – 5.5 V2 kΩ15 pFOpenN/A
ten, tdisEnable time, disable time1.1 V – 1.6 V2 kΩ15 pF2 × VCCO0.1 V
1.65 V – 2.7 V2 kΩ15 pF2 × VCCO0.15 V
3.0 V – 5.5 V2 kΩ15 pF2 × VCCO0.3 V
ten, tdisEnable time, disable time1.1 V – 1.6 V2 kΩ15 pFGND0.1 V
1.65 V – 2.7 V2 kΩ15 pFGND0.15 V
3.0 V – 5.5 V2 kΩ15 pFGND0.3 V
GUID-700B4291-5E2B-4290-8EA1-6E2EF85823D8-low.gif
  1. VCCI is the supply pin associated with the input port.
  2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
Figure 7-2 Propagation Delay
GUID-204D789D-036A-4CF7-882A-1640F8046C85-low.gif
  1. VCCI is the supply pin associated with the input port.
  2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
Figure 7-3 Input Transition Rise and Fall Rate
GUID-4ECE29F0-D29D-4CE4-87E3-116AA2528745-low.gif
  1. Illustrative purposes only. Enable time is a calculation as described in Enable Times.
  2. Output waveform on the condition that input is driven to a valid Logic low.
  3. Output waveform on the condition that input is driven to a valid Logic high.
  4. VCCI is the supply pin associated with the input port.
  5. VCCO is the supply pin associated with the output port.
  6. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
Figure 7-4 Enable Time And Disable Time