SLLSE57E April   2011  – March 2015 SN75DP130

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Power Dissipation
    6. 7.6 Electrical Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Reset Signal
      2. 9.3.2 Hot Plug Detect and Cable Adapter Detect
      3. 9.3.3 AUX and DDC Configuration
      4. 9.3.4 Main Link Configuration
      5. 9.3.5 Link Training and DPCD
      6. 9.3.6 Equalization
      7. 9.3.7 Configurable Outputs
      8. 9.3.8 Squelch
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 I2C Interface Overview
    6. 9.6 Register Maps
      1. 9.6.1 SN75DP130 Local I2C Control and Status Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Logic I2C Interface
        2. 10.2.2.2 CAD Sink Over Ride
        3. 10.2.2.3 HPD Sink Over Ride
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 SN75DP130 Power Sequencing
      1. 11.1.1 Power-Up Sequence:
      2. 11.1.2 Power-Down Sequence:
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Layer Stack
      2. 12.1.2 Differential Traces
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • Supports DP v1.1a and DP v1.2 Signaling Including HBR2 Data Rates to 5.4 Gbps
  • Supports HDMI 1.4b With TMDS Clock Frequencies up to 340 MHz
  • Glueless Interface to AMD, Intel, and NVIDIA Graphics Processors
  • Auto-Configuration Through Link Training
  • Output Signal Conditioning With Tunable Voltage Swing and Pre-Emphasis Gain
  • Highly Configurable Input Variable Equalizer
  • Two Device Options Including a Dual Power Supply Configuration for Lowest Power
  • 2-kV ESD HBM Protection
  • Temperature Range: 0°C to 85°C
  • 48-Pin 7-mm × 7-mm VQFN Package

2 Applications

  • Notebook PCs
  • Desktop PCs
  • PC Docking Stations
  • PC Standalone Video Cards

3 Description

The SN75DP130 device is a single channel DisplayPort™ (DP) re-driver that regenerates the DP high-speed digital link. The device complies with the VESA DisplayPort Standard Version 1.2, and supports a 4-lane Main Link interface signaling up to HBR2 rates at 5.4 Gbps per lane. This device also supports DP++ Dual-Mode, offering TMDS signaling for DVI and full HDMI Version 1.4a support.

The device compensates for PCB-related frequency loss and switching-related loss to provide the optimum DP electrical performance from source to sink. The Main Link signal inputs feature configurable equalizers with selectable boost settings. At the Main Link output, four primary levels of differential output voltage swing (VOD) and four primary levels of pre-emphasis are available. A secondary level of boost adjustment, programmed through I2C, for fine-tuning the Main Link output. The device can monitor the AUX channel and automatically adjust the output signaling levels and input equalizers in response to Link Training commands. Additionally, the SN75DP130 output signal conditioning and EQ parameters are fully programmable through the I2C interface.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN75DP130 VQFN (48) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simple Application

SN75DP130 app_photo_FP_llse57.gif