JAJSPZ7E
november 2002 – march 2023
SN65HVD08
,
SN75HVD08
PRODUCTION DATA
1
特長
2
アプリケーション
3
説明
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Driver Switching Characteristics
6.7
Receiver Switching Characteristics
6.8
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.1.1
Supply Source Impedance
9.1.2
Opto-Isolated Data Buses
9.1.3
Opto Alternative
9.2
Typical Application
9.2.1
Design Requirements
9.2.1.1
Data Rate and Bus Length
9.2.1.2
Stub Length
30
31
9.2.1.3
Bus Loading
9.2.1.4
Receiver Failsafe
9.2.2
Detailed Design Procedure
9.2.3
Application Curve
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Device Support
10.1.1
サード・パーティ製品に関する免責事項
10.2
サポート・リソース
10.3
Trademarks
10.4
静電気放電に関する注意事項
10.5
用語集
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
D|8
MSOI002K
P|8
MPDI001B
サーマルパッド・メカニカル・データ
発注情報
jajspz7e_oa
jajspz7e_pm
7
Parameter Measurement Information
Figure 7-1
Driver V
OD
With Common-Mode Loading Test Circuit
Figure 7-2
Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Figure 7-3
Driver Switching Test Circuit and Voltage Waveforms
Figure 7-4
Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
Figure 7-5
Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
Figure 7-6
Receiver Switching Test Circuit and Voltage Waveforms
Figure 7-7
Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
Figure 7-8
Receiver Enable Time From Standby (Driver Disabled)