SLLS846C May 2009 – August 2014 SN75LVDS83B
PRODUCTION DATA.
FlatLink™ is an LVDS SerDes data transmission system. The SN75LVDS83B takes in three (or four) data words each containing seven single-ended data bits and converts this to an LVDS serial output. Each serial output runs at seven times that of the parallel data rate. The deserializer (receiver) device operates in the reverse manner. The three (or four) LVDS serial inputs are transformed back to the original seven-bit parallel single-ended data. FlatLink™ devices are available in 21:3 or 28:4 SerDes ratios.
The data inputs to the transmitter come from the graphics processor and consist of up to 24 bits of video information, a horizontal synchronization bit, a vertical synchronization bit, an enable bit, and a spare bit. The data can be loaded into the registers upon either the rising or falling edge of the input clock selectable by the CLKSEL pin. Data inputs are 1.8 V to 3.3 V tolerant for the SN75LVDS83B and can connect directly to low-power, low-voltage application and graphic processors. The bit mapping is listed in Table 1.
RED | GREEN | BLUE | |
---|---|---|---|
LSB | R0 | G0 | B0 |
R1 | G1 | B1 | |
R2 | G2 | B2 | |
4-bit MSB | R3 | G3 | B3 |
R4 | G4 | B4 | |
6-bit MSB | R5 | G5 | B5 |
R6 | G6 | B6 | |
8-bit MSB | R7 | G7 | B7 |
The pixel data assignment is listed in Table 2 for 24-bit, 18-bit, and 12-bit color hosts.
SERIAL CHANNEL | DATA BITS | 8-BIT | 6-BIT | 4-BIT | |||
---|---|---|---|---|---|---|---|
FORMAT-1 | FORMAT-2 | FORMAT-3 | NON-LINEAR STEP SIZE | LINEAR STEP SIZE | |||
Y0 | D0 | R0D27 | R2 | R2 | R0 | R2 | VCC |
D1 | R1 | R3 | R3 | R1 | R3 | GND | |
D2 | R2 | R4 | R4 | R2 | R0 | R0 | |
D3 | R3 | R5 | R5 | R3 | R1 | R1 | |
D4 | R4 | R6 | R6 | R4 | R2 | R2 | |
D6 | R5 | R7 | R7 | R5 | R3 | R3 | |
D7 | G0 | G2 | G2 | G0 | G2 | VCC | |
Y1 | D8 | G1 | G3 | G3 | G1 | G3 | GND |
D9 | G2 | G4 | G4 | G2 | G0 | G0 | |
D12 | G3 | G5 | G5 | G3 | G1 | G1 | |
D13 | G4 | G6 | G6 | G4 | G2 | G2 | |
D14 | G5 | G7 | G7 | G5 | G3 | G3 | |
D15 | B0 | B2 | B2 | B0 | B2 | VCC | |
D18 | B1 | B3 | B3 | B1 | B3 | GND | |
Y2 | D19 | B2 | B4 | B4 | B2 | B0 | B0 |
D20 | B3 | B5 | B5 | B3 | B1 | B1 | |
D21 | B4 | B6 | B6 | B4 | B2 | B2 | |
D22 | B5 | B7 | B7 | B5 | B3 | B3 | |
D24 | HSYNC | HSYNC | HSYNC | HSYNC | HSYNC | HSYNC | |
D25 | VSYNC | VSYNC | VSYNC | VSYNC | VSYNC | VSYNC | |
D26 | ENABLE | ENABLE | ENABLE | ENABLE | ENABLE | ENABLE | |
Y3 | D27 | R6 | R0 | GND | GND | GND | GND |
D5 | R7 | R1 | GND | GND | GND | GND | |
D10 | G6 | G0 | GND | GND | GND | GND | |
D11 | G7 | G1 | GND | GND | GND | GND | |
D16 | B6 | B0 | GND | GND | GND | GND | |
D17 | B7 | B1 | GND | GND | GND | GND | |
D23 | RSVD | RSVD | GND | GND | GND | GND | |
CLKOUT | CLKIN | CLK | CLK | CLK | CLK | CLK | CLK |
The transmission of data bits D0 through D27 occurs as each are loaded into registers upon the edge of the CLKIN signal, where the rising or falling edge of the clock may be selected via CLKSEL. The selection of a clock rising edge occurs by inputting a high level to CLKSEL, which is achieved by populating pull-up resistor to pull CLKSEL=high. Inputting a low level to select a clock falling edge is achieved by directly connecting CLKSEL to GND.
The SN75LVDS83B can be put in low-power consumption mode by active-low input SHTDN#. Connecting pin SHTDN# to GND will inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level. Populate a pull-up to VCC on SHTDN# to enable the device for normal operation.