SBFS022C June   2003  – October 2015 SRC4192 , SRC4193

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Port Operation
      2. 7.3.2 Output Port Operation
      3. 7.3.3 Soft Mute Function
      4. 7.3.4 Digital Attenuation (SRC4193 Only)
      5. 7.3.5 Ready Output
      6. 7.3.6 Ratio Output (SRC4193 Only)
      7. 7.3.7 Serial Peripheral Interface (SPI) Port: SRC4193 Only
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset and Power Down Operation
      2. 7.4.2 Audio Port Modes
      3. 7.4.3 Bypass Mode
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Interfacing to Digital Audio Receivers and Transmitters
      2. 8.1.2 TDM Applications
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Control Method
        2. 8.2.2.2 Audio Input and Output
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Reference Clock
      2. 10.1.2 Pin Compatibility With the Analog Devices AD1896 (SRC4192 Only)
        1. 10.1.2.1 Crystal Oscillator
        2. 10.1.2.2 Reference Clock Frequency
        3. 10.1.2.3 Master Mode Maximum Sampling Frequency
        4. 10.1.2.4 Matched Phase Mode
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

This section of the data sheet provides practical applications information for hardware and systems engineers designing the SRC4192 and SRC4193 devices into the end equipment.

8.1.1 Interfacing to Digital Audio Receivers and Transmitters

The input and output ports of the SRC4192 and SRC4193 devices are designed to interface to a variety of audio devices, including receivers and transmitters commonly used for AES/EBU, S/PDIF, and CP1201 communications.

Texas Instruments manufactures the DIR1703 digital audio interface receiver and DIT4096/4192 digital audio transmitters to address these applications.

Figure 70 shows interfacing the DIR1703 device to the input port of the SRC4192 or SRC4193 device. The DIR1703 device operates from a single 3.3-V supply, which requires the VIO supply (pin 7) for the SRC4192 or SRC4193 device to be set to 3.3 V for interface compatibility.

SRC4192 SRC4193 intf_src4193_dir1703.gif Figure 70. Interfacing the SRC4193 to the DIR1703 Digital Audio Interface Receiver

Figure 71 shows the interface between the output port of the SRC4192 or SRC4193 device and the audio serial port of the DIT4096 or DIT4192 device. Again, the VIO supplies for both the SRC419x device and DIT4096/4192 device are set to 3.3 V for compatibility.

SRC4192 SRC4193 intf_src4193_dit4096.gif Figure 71. Interfacing the SRC4193 to the DIT4096/4192 Digital Audio Interface Transmitter

Like the output port of the SRC4192 or SRC4193 device, the audio serial port of the DIT4096 and DIT4192 device can be configured as a master or slave. In cases where the output port of the SRC419x device is set to master mode, use the reference clock source (RCKI) as the master clock source (MCLK) for the DIT4096/4192 device, to ensure that the transmitter is synchronized to the output port data of the SRC419x device.

8.1.2 TDM Applications

The SRC4192 and SRC4193 devices support a TDM output mode, which allows multiple devices to be daisy-chained together to create a serial frame. Each device occupies one subframe within a frame, and each sub-frame carries two channels (Left followed by Right). Each sub-frame is 64 bits long, with 32 bits allotted for each channel. The audio data for each channel is left justified within the allotted 32 bits. Figure 72 shows the TDM frame format, while Figure 73 shows TDM input timing parameters, which are listed in Electrical Characteristics.

SRC4192 SRC4193 tdm_frame_format.gif Figure 72. TDM Frame Format
SRC4192 SRC4193 input_timing_tdm_mode.gif Figure 73. Input Timing for TDM Mode

The frame rate is equal to the output sampling frequency, fs. The BCKO frequency for the TDM interface is N × 64fs, where N is the number of devices included in the daisy chain. For Master mode, the output BCKO frequency is fixed to the reference clock (RCKI) input frequency. The number of devices that can be daisy-chained in TDM mode is dependent upon the output sampling frequency and the BCKO frequency, leading to the following numerical relationship:

Equation 1. Number of Daisy-Chained Devices = (fBCKO / fs) / 64

where

  • fBCKO = Output Port Bit Clock (BCKO), 27.648-MHz maximum
  • fs = Output Port Sampling (or LRCKO) Frequency, 216-kHz maximum.

This relationship holds true for both slave and master modes.

Figure 74 and Figure 75 show typical connection schemes for TDM mode. Although the TMS320C671x DSP device family is shown as the audio processing engine in these figures, other TI digital signal processors with a multi-channel buffered serial port (McBSPTM) may also function with this arrangement. Interfacing to processors from other manufacturers is also possible. Refer to Figure 62 in this data sheet, along with the equivalent serial port timing diagrams shown in the DSP data sheet, to determine compatibility.

SRC4192 SRC4193 tdm_if_dev_slaves.gif Figure 74. TDM Interface where all Devices are Slaves
SRC4192 SRC4193 tdm_if_one_dev_master.gif Figure 75. TDM Interface where one Device is Master to Multiple Slaves

8.2 Typical Application

Figure 76 and Figure 77 show typical connection diagrams for the SRC4192 and SRC4193 devices (respectively). Recommended values for power supply bypass capacitors are included. These capacitors should be placed as close to the IC package as possible.

SRC4192 SRC4193 typapp_1.gif Figure 76. Typical Connection Diagram for the SRC4192
SRC4192 SRC4193 typapp_2.gif Figure 77. Typical Connection Diagram for the SRC4193

8.2.1 Design Requirements

The following lists design requirements:

  • Control: Hardware, I2C, or SPI
  • Audio input: PCM serial data
  • Audio output: PCM serial data
  • Reference clock

8.2.2 Detailed Design Procedure

8.2.2.1 Control Method

The SRC4192 is a hardware controlled device while the SRC4193 is a software controlled device. The SRC4192 control pins can be connected to VDD or GND directly or by the GPIO of a host controller. The SRC4193 can communicate over a 3 wire SPI.

8.2.2.2 Audio Input and Output

The Audio input and output ports can handle 16, 18, 20, or 24 bit right justified PCM serial data as well as 24 bit I2S or left justified PCM serial data at up to a 212-kHz sampling rate. A TDM format is also available. Both input and output can operate in slave mode, or one can operate as master while the other operates as a slave. A 16:1 or 1:16 is the max ratio supported between the input and output audio sampling rates.

8.2.3 Application Curves

SRC4192 SRC4193 sbfs022_typchar_5.gif
44.1 kHz:48 kHz
Figure 78. FFT With 1-kHz Input Tone at 0 dBFS
SRC4192 SRC4193 sbfs022_typchar_7.gif
44.1 kHz:96 kHz
Figure 79. FFT With 1-kHz Input Tone at 0 dBFS