SBFS022C June   2003  – October 2015 SRC4192 , SRC4193

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Port Operation
      2. 7.3.2 Output Port Operation
      3. 7.3.3 Soft Mute Function
      4. 7.3.4 Digital Attenuation (SRC4193 Only)
      5. 7.3.5 Ready Output
      6. 7.3.6 Ratio Output (SRC4193 Only)
      7. 7.3.7 Serial Peripheral Interface (SPI) Port: SRC4193 Only
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset and Power Down Operation
      2. 7.4.2 Audio Port Modes
      3. 7.4.3 Bypass Mode
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Interfacing to Digital Audio Receivers and Transmitters
      2. 8.1.2 TDM Applications
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Control Method
        2. 8.2.2.2 Audio Input and Output
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Reference Clock
      2. 10.1.2 Pin Compatibility With the Analog Devices AD1896 (SRC4192 Only)
        1. 10.1.2.1 Crystal Oscillator
        2. 10.1.2.2 Reference Clock Frequency
        3. 10.1.2.3 Master Mode Maximum Sampling Frequency
        4. 10.1.2.4 Matched Phase Mode
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DB|28
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

SRC4192 DB Package
28-Pin SSOP
Top View
SRC4192 SRC4193 src4192_po.gif
SRC4193 DB Package
28-Pin SSOP
Top View
SRC4192 SRC4193 src4193_po.gif

Pin Functions

PIN I/O DESCRIPTION
NAME SRC4192 SRC4193
BCKI 5 5 I Input port bit clock I/O
BCKO 25 25 O Output port bit clock I/O
BYPAS 9 9 I ASRC bypass control input (Active High)
CCLK — 27 I SPI port data clock input
CDATA — 28 I SPI port serial data input
CS — 26 I SPI port chip select input (Active Low)
DGND 8, 21 8, 21 – Digital ground
IFMT0 10 — I Input port data format control input
IFMT1 11 — I Input port data format control input
IFMT2 12 — I Input port data format control input
LGRP 1 — I Low group delay control input (active high)
LRCKI 6 6 I Input port left/right word clock I/O
LRCKO 24 24 O Output port left/right word clock I/O
MODE0 26 — I Serial port mode control input
MODE1 27 — I Serial port mode control input
MODE2 28 — I Serial port mode control input
MUTE 14 14 I Output mute control input (active high)
NC 3 2,3,10,11,12,17,18,19 – No connection
OFMT0 19 — I Output port data format control input
OFMT1 18 — I Output port data format control input
OWL0 17 — I Output port data word length control input
OWL1 16 — I Output port data word length control input
RATIO — 16 O

Input-to-output ratio flag output

Low output denotes output rate lower than input rate.

High output denotes output rate higher than input rate.
RCKI 2 1 I Reference Clock Input
RDY 15 15 O ASRC Ready Status Output (Active Low)
RST 13 13 I Reset Input (Active Low)
SDIN 4 4 I Audio Serial Data Input
SDOUT 23 23 O Audio Serial Data Output
TDMI 20 20 I TDM Data Input (Connect to DGND when not in use)
VDD 22 22 I Digital Core Supply, 3.3 V
VIO 7 7 I Digital I/O Supply, 1.65 V to VDD