The device has many supported features and flexible options that can be used in the system to seamlessly connect multiple TAC5111-Q1 devices by sharing a single common I²C or SPI control bus and an audio serial interface bus. This architecture enables multiple applications to be applied to a system that require a microphone or speaker array for beam-forming operation, audio conferencing, noise cancellation, and so forth. Figure 7-14 shows a diagram of multiple TAC5111-Q1 devices in a configuration where the control and audio data buses are shared.

Figure 7-14 Multiple TAC5111-Q1 Devices With Shared Control and Audio Data Buses

The TAC5111-Q1 consists of the following features to enable seamless connection and interaction of multiple devices using a shared bus:

• Supports up to four pin-programmable I²C target addresses
• I²C broadcast simultaneously writes to (or triggers) all TAC5111-Q1 devices
• Supports up to 32 configuration input/output channel slots for the audio serial interface
• Tri-state feature (with enable and disable) for the unused audio data slots of the device
• Supports a bus-holder feature (with enable and disable) to keep the last driven value on the audio bus
• The GPIOx, GPI1 or GPO1 pin can be configured as a secondary input/output data lane or as a secondary audio serial interface
• The GPIOx, GPI1 or GPO1 pin can be used in a daisy-chain configuration of multiple TAC5111-Q1 devices
• Supports one BCLK cycle data latching timing to relax the timing requirement for the high-speed interface
• Programmable controller and target options for both primary and secondary audio serial interface
• Ability to synchronize the multiple devices for the simultaneous sampling requirement across devices
• Inter Channel Gain Alignment(ICGA) feature to align the DAC Channel gain across devices.