JAJSNO3 January 2022 TAC5111
ADVANCE INFORMATION
Table 7-149 lists the memory-mapped registers for the TAC5212 registers. All register offset addresses not listed in Table 7-149 should be considered as reserved locations and the register contents should not be modified.
PAGE_CFG is shown in Table 7-150.
Return to the Summary Table.
The device memory map is divided into pages. This register sets the page.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | PAGE[7:0] | R/W | 00000000b | These bits set the device page.
0d = Page 0 1d = Page 1 2d to 254d = Page 2 to page 254 respectively 255d = Page 255 |
DSP_CFG0 is shown in Table 7-151.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
6 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
5 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
4 | RESERVED | R | 0b | Reserved bit; Write only reset value |
3 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
2 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
1 | DIS_DVOL_OTF_CHG | R/W | 0b | Disable run-time changes to DVOL settings.
0d = Digital volume control changes supported while ADC is powered-on 1d = Digital volume control changes not supported while ADC is powered-on. |
0 | EN_BQ_OTF_CHG | R/W | 0b | Enable run-time changes to Biquad settings.
0d = Disable on the fly biquad changes 1d = Enable on the fly biquad changes |
CLK_CFG0 is shown in Table 7-152.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CNT_TGT_CFG_OVR_PASI | R/W | 0b | ASI controller target Config Override Register
0d = controller-target Config as per PASI_CNT_CFG bit. 1d = Override the standard behavior of the PASI_CNT_CFG. In this case the clock auto detect feature is not available. PASI_CNT_CFG = 0 : BCLK is input but FSYNC is output. PASI_CNT_CFG = 1 : BCLK is output but FSYNC in input. |
6 | CNT_TGT_CFG_OVR_SASI | R/W | 0b | ASI controller target Config Override Register
0d = controller-target Config as per SASI_CNT_CFG bit. 1d = Override the standard behavior of the SASI_CNT_CFG. In this case the clock auto detect feature is not available. SASI_CNT_CFG = 0 : BCLK is input but FSYNC is output. SASI_CNT_CFG = 1 : BCLK is output but FSYNC in input. |
5 | RESERVED | R | 0b | Reserved bit; Write only reset value |
4-3 | RESERVED | R/W | 00b | Reserved bits; Write only reset values |
2 | PASI_USE_INT_FSYNC | R/W | 0b | For Primary use internal FSYNC in controller mode configuration.
0d = Use external FSYNC 1d = Use internal FSYNC |
1 | SASI_USE_INT_FSYNC | R/W | 0b | For Secondary use internal FSYNC in controller mode configuration.
0d = Use external FSYNC 1d = Use internal FSYNC |
0 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
CHANNEL_CFG1 is shown in Table 7-153.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | FORCE_DYN_MODE_CUST_MAX_CH | R/W | 0b | ADC Force dynamic mode custom max channel
0d = In Dynamicmode , Max channel is based on ADC_DYN_MAXCH_SEL 1d = In Dynamic mode, max channel is custom as DYN_MODE_CUST_MAX_CH |
6-3 | DYN_MODE_CUST_MAX_CH[3:0] | R/W | 0000b | ADC Dynamic mode custom max channel configuration
[3]->CH4_EN [2]->CH3_EN [1]->CH2_EN [0]->CH1_EN |
2-0 | RESERVED | R | 000b | Reserved bits; Write only reset values |
CHANNEL_CFG2 is shown in Table 7-154.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DAC_FORCE_DYN_MODE_CUST_MAX_CH | R/W | 0b | DAC Force dynamic mode custom max channel
0d = In Dynamic, Max channel is based on DAC_DYN_MAXCH_SEL 1d = In Dynamic mode, max channel is custom as per DAC_DYN_MODE_CUST_MAX_CH |
6-3 | DAC_DYN_MODE_CUST_MAX_CH[3:0] | R/W | 0000b | DAC Dynamic mode custom max channel configuration ([3]->CH4_EN, [2]->CH3_EN, [1]->CH2_EN, [0]->CH1_EN)
[3]->CH4_EN [2]->CH3_EN [1]->CH2_EN [0]->CH1_EN |
2-0 | RESERVED | R | 000b | Reserved bits; Write only reset values |
SRC_CFG0 is shown in Table 7-155.
Return to the Summary Table.
This register is configuration register 1 for SRC.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SRC_EN | R/W | 0b | SRC enable config
0b = SRC disable 1b = SRC enable |
6 | DIS_AUTO_SRC_DET | R/W | 0b | SRC auto detect config
0b = SRC auto detect enabled 1b = SRC auto detect disabled |
5-0 | RESERVED | R | 000000b | Reserved bits; Write only reset value |
SRC_CFG1 is shown in Table 7-156.
Return to the Summary Table.
This register is configuration register 2 for SRC.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | MAIN_FS_CUSTOM_CFG | R/W | 0b | Main Fs custom config
0b = Main Fs is auto inferred 1b = Main Fs need to be selected from MAIN_FS_SELECT_CFG |
6 | MAIN_FS_SELECT_CFG | R/W | 0b | Main Fs select config
0b = PASI Fs shall be used as Main Fs 1b = SASI Fs shall be used as Main Fs |
5-3 | MAIN_AUX_RATIO_M_CUSTOM_CFG[2:0] | R/W | 000b | Main and Aux Fs Ratio m:n config
0d = m is auto inferred 1d = 1 2d = 2 3d = 3 4d = 4 5d = Reserved 6d = 6 7d = Reserved |
2-0 | MAIN_AUX_RATIO_N_CUSTOM_CFG[2:0] | R/W | 000b | Main and Aux Fs Ratio m:n config
0d = n is auto inferred 1d = 1 2d = 2 3d = 3 4d = 4 5d = Reserved 6d = 6 7d = Reserved |
JACK_DET_CFG0 is shown in Table 7-157.
Return to the Summary Table.
This register is the JACK DET configuration register 0.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | JACK_DET_MONITOR_FREQ[1:0] | R/W | 00b | Headset Detection Pulse Frequency
0d = 0.5 Hz 1d = 1 Hz 2d = 7.5 Hz 3d = 15 Hz |
5 | JACK_DET_PULSE_WIDTH | R/W | 0b | Detector Pulse High Width
0d = 4ms (MICBIAS PIN Cap = 1 uF) 1d = 32ms (MICBIAS PIN Cap = 10 uF) |
4 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
3 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
2-1 | HPDET_CLOCK_SEL[1:0] | R/W | 00b | Headphone Detection Clock Timeperiod Select
0d = 1ms 1d = 2ms 2d = 4ms 3d = Reserved |
0 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
JACK_DET_CFG1 is shown in Table 7-158.
Return to the Summary Table.
This register is the JACK DET configuration register 1.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
6 | JACK_DET_COMP_CTRL2 | R/W | 0b | Hook Press Threshold Control in Fixed External Resistance case, controls the choice of Lowest Microphone impedance to be supported or Highest Hook button Impedance to be supported
0d = Minimum Microphone resistance supported, R_Mic = 800 Ωs and Max Hook button impedance supported, R_Hook = 320 Ωs for AC coupled Headphones R26<3> = 0 (else, when R26<3> = 1, R_hook = 150 Ωs) 1d = Max Hook button impedance supported, R_hook = 680 Ωs and Minimum Microphone resistance supported, R_Mic = 1350 Ωs for AC coupled Headphones R26<3> = 0 (else, when R26<3> = 1, R_Mic = 1750 Ωs) |
5-4 | JACK_DET_COMP_CTRL3[1:0] | R/W | 00b | Hook Pressed Jack Insertion support, valid only for External Resistor Type P0_R25_D4 = 0 else Don't care.
0d = supports minimum Hook button impedance of 150 Ωs for Hook Pressed Jack Insertion detection 1d = supports minimum Hook button impedance of 100 Ωs for Hook Pressed Jack Insertion detection 2d = supports minimum Hook button impedance of 50 Ωs for Hook Pressed Jack Insertion detection 3d = Reserved |
3 | HPDET_COUPLING | R/W | 0b | Headphone detect coupling
0d = AC coupled 1d = DC coupled |
2 | HPDET_USE_2x_CURR | R/W | 0b | Headset detect current sel config
0d = 2x current for headphone detection disabled 1d = 2x current for headphone detection enabled |
1 | JACK_DET_EN | R/W | 0b | Headset Detection Enable
0d = Headset Detection Disabled 1d = Headset Detection Enabled |
0 | RESERVED | R | 0b | Reserved bit; Write only reset value |
JACK_DET_CFG2 is shown in Table 7-159.
Return to the Summary Table.
This register is the JACK DET configuration register 2.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0b | Reserved bit; Write only reset value |
6 | HPDET_DEB | R/W | 0b | Headphone Detection Debounce Programmability
0d = No Debounce 1d = Debounce of 3 detections |
5-3 | JACK_DET_DEB_INSERT[2:0] | R/W | 000b | Headset Insert Detection Debounce Programmability
0d = Debounce Time = 16ms 1d = Debounce Time = 32ms 2d = Debounce Time = 64ms 3d = Debounce Time = 128ms 4d = Debounce Time = 256ms 5d = Debounce Time = 512ms 6d = Reserved. Don not use 7d = No Debounce |
2 | JACK_DET_DEB_REMOVAL | R/W | 0b | Headset Removal Detection Debounce Programmability
0d = Debounce of 5 detections 1d = Debounce of 3 detections |
1-0 | JACK_DET_DEB_HOOK_PRESS[1:0] | R/W | 00b | Hook Press Debounce config
0d = No Debounce 1d = No Debounce 2d = Debounce of 2 detections 3d = Debounce of 3 detections |
JACK_DET_CFG3 is shown in Table 7-160.
Return to the Summary Table.
This register is the JACK DET configuration register 3.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | JACK_TYPE_FLAG[1:0] | R | 00b | Headset Jack type flag
0d = Jack is not inserted 1d = Jack is inserted without Microphone 2d = Reserved. Do not use 3d = Jack is inserted with Microphone |
5-4 | HEADSET_TYPE_DET[1:0] | R | 00b | Headset type
0d = Headset is not inserted 1d = Jack is inserted with mono-HS (RIGHT) 2d = Jack is inserted with mono-HS (LEFT) 3d = Jack is inserted with stereo-HS |
3-0 | RESERVED | R | 0000b | Reserved bits; Write only reset value |
LPAD_CFG1 is shown in Table 7-161.
Return to the Summary Table.
Low Power Activity Detection. Voice activity detection or Ultrasonic Activity detection configuration register 1
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | LPAD_MODE[1:0] | R/W | 00b | Auto ADC power up / power down configuration selection.
0d = User initiated ADC power-up and ADC power-down 1d = VAD/UAD interrupt based ADC power up and ADC power down 2d = VAD/UAD interrupt based ADC power up but user initiated ADC power down Dont use |
5-4 | LPAD_CH_SEL[1:0] | R/W | 10b | VAD channel select.
0d = Channel 1 is monitored for VAD/UAD activity 1d = Channel 2 is monitored for VAD/UAD activity 2d = Channel 3 is monitored for VAD/UAD activity 3d = Channel 4 is monitored for VAD/UAD activity |
3 | LPAD_SDOUT_INT_CFG | R/W | 0b | SDOUT interrupt configuration.
0d = SDOUT pin is not enabled for interrupt function 1d = SDOUT pin is enabled to support interrupt output when channel data in not being recorded |
2 | RESERVED | R | 0b | Reserved bit; Write only reset value |
1 | LPAD_PD_DET_EN | R/W | 0b | Enable ASI output data during VAD/UAD activity.
0d = VAD/UAD processing is not enabled during ADC recording 1d = VAD/UAD processing is enabled during ADC recording and VAD interrupts are generated as configured |
0 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
LPSG_CFG1 is shown in Table 7-162.
Return to the Summary Table.
Low Power Signal Generation configuration register 1
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | LPSG_CH_SEL[1:0] | R/W | 10b | LPSG channel select.- UAG
0d = UAG activity is generated on channel 1 1d = UAG activity is generated on channel 2 2d = UAG activity is generated on channel 3 3d = UAG activity is generated on channel 4 |
5 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
4-0 | RESERVED | R | 00000b | Reserved bits; Write only reset values |
LPAD_LPSG_CFG1 is shown in Table 7-163.
Return to the Summary Table.
This register is configuration register 1 for VAD/UAD/UAG.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | LPAD_LPSG_CLK_CFG[1:0] | R/W | 00b | Clock select for VAD/UAD/UAG
0d = VAD/UAD/UAG processing using internal oscillator clock 1d = VAD/UAD/UAG processing using external clock on BCLK input 2d = VAD/UAD/UAG processing using external clock on CCLK input 3d = Custom clock configuration based on CNT_CFG, CLK_SRC and CLKGEN_CFG registers in page 0 |
5-4 | LPAD_LPSG_EXT_CLK_CFG[1:0] | R/W | 00b | Clock configuration using external clock for VAD/UAD/UAG
0d = External clock is 24.576 MHz 1d = External clock is 6.144 MHz 2d = External clock is 12.288 MHz 3d = External clock is 18.432 MHz |
3 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
2 | LPAD_PH1_EN | R/W | 0b | Enable LPAD Phase 1 detection through Jack Detection comparator.
0d = LPAD phase 1 diabled 1d = LPAD phase 1 enabled |
1-0 | RESERVED | R | 00b | Reserved bits; Write only reset values |
LIMITER_CFG is shown in Table 7-164.
Return to the Summary Table.
This register is configuration register 2 for Limiter.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | LIMITER_INP_SEL[1:0] | R/W | 00b | Limiter input select config
0d = max(dacin_ch0, dacin_ch1) 1d = dacin_ch1 2d = dacin_ch0 3d = avg(dacin_ch0, dacin_ch1) |
5-4 | LIMITER_OUT_SEL[1:0] | R/W | 00b | Limiter output select config
0d = applied on both 1d = dacin_ch1 2d = dacin_ch0 3d = applied none |
3-0 | RESERVED | R | 0000b | Reserved bits; Write only reset values |
AGC_DRC_CFG is shown in Table 7-165.
Return to the Summary Table.
This register is configuration register 2 for AGC_DRC.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | AGC_CH1_EN | R/W | 0b | AGC Channel 1 enable config
0d = disable 1d = enable |
6 | AGC_CH2_EN | R/W | 0b | AGC Channel 2 enable config
0d = disable 1d = enable |
5 | AGC_CH3_EN | R/W | 0b | AGC Channel 3 enable config
0d = disable 1d = enable |
4 | AGC_CH4_EN | R/W | 0b | AGC Channel 4 enable config
0d = disable 1d = enable |
3 | DRC_CH1_EN | R/W | 0b | DRC Channel 1 enable config
0d = disable 1d = enable |
2 | DRC_CH2_EN | R/W | 0b | DRC Channel 2 enable config
0d = disable 1d = enable |
1 | DRC_CH3_EN | R/W | 0b | DRC Channel 3 enable config
0d = disable 1d = enable |
0 | DRC_CH4_EN | R/W | 0b | DRC Channel 4 enable config
0d = disable 1d = enable |
PLIM_CFG0 is shown in Table 7-166.
Return to the Summary Table.
This register is configuration register 0 for PLIM.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | EN_PLIM | R/W | 0b | Enable PLIM
0d = Disable 1d = Enable |
6-4 | PLIM_ATTN_VAL[2:0] | R/W | 000b | PLIM attenuation factor
0d = 0dB 1d = -6dB 2d = -12dB 3d = -18dB 4d = -24dB 5d = -30dB 6d = -36dB 7d = -42dB |
3 | PLIM_BY_SAR_GPA | R/W | 0b | PLIM attenuation value source
0d = Plimit attentation based on GPIO and reg_plimi_attn_val 1d = Plimit attenuation based on GPA Analog voltage. LUT will map SAR ADC data to Attenuation factor |
2 | PLIM_RECOVERY | R/W | 0b | PLIM attenuation recovery
0d = Plimit func doesn’t recover. It stays at same attenuation level or can apply more attenuation if required 1d = Plimit func recovers (reduces the attenuation) if “gpio_val=0” or “sar_adc_gpa” data suggest that Battery Voltage has recovered then we can reduce the attenuation being applied |
1-0 | RESERVED | R | 00b | Reserved bits; Write only reset value |
MIXER_CFG0 is shown in Table 7-167.
Return to the Summary Table.
This register is the MISC configuration register 0.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | EN_DAC_ASI_MIXER | R/W | 0b | Enable DAC ASI Mixer
0b = Disabled 1b = Enabled |
6 | EN_SIDE_CHAIN_MIXER | R/W | 0b | Enable Side Chain Mixer
0b = Disabled 1b = Enabled |
5 | EN_ADC_CHANNEL_MIXER | R/W | 0b | Enable ADC Channel Mixer
0b = Disabled 1b = Enabled |
4 | EN_LOOPBACK_MIXER | R/W | 0b | Enable Loopback Mixer
0b = Disabled 1b = Enabled |
3-0 | RESERVED | R | 0000b | Reserved bits; Write only reset value |
MISC_CFG0 is shown in Table 7-168.
Return to the Summary Table.
This register is the MISC configuration register 0.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | EN_DISTORTION | R/W | 0b | Distortion Limiter enable config
0b = Distortion Limiter disable 1b = Distortion Limiter enable |
6 | EN_BOP | R/W | 0b | BOP enable config
0b = BOP disable 1b = BOP enable |
5 | EN_THERMAL_FOLDBACK | R/W | 0b | Thermal Foldback enable config
0b = Thermal Foldback disable 1b = Thermal Foldback enable |
4 | EN_DRC | R/W | 0b | DRC enable config
0b = DRC disable 1b = DRC enable |
3 | DAC_SIGNAL_GENERATOR_1_ENABLE | R/W | 0b | DAC signal generator 1 enable config
0b = Signal generator disabled 1b = Signal generator enabled |
2 | DAC_SIGNAL_GENERATOR_2_ENABLE | R/W | 0b | DAC signal generator 2 enable config
0b = Signal generator disabled 1b = Signal generator enabled |
1 | DSP_VBAT_AVDD_SEL | R/W | 0b | SAR data source select for DSP Limiter, BOP, DRC
0b = SAR VBAT data to DSP 1b = SAR AVDD data to DSP |
0 | BRWNOUT_EN | R/W | 0b | Brownout enable config
0b = Brownout disable 1b = Brownout enable |
BRWNOUT is shown in Table 7-169.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | BRWNOUT_THRS[7:0] | R/W | 10111111b | Threshold for brownout shutdown (IF P1_R45_D1->DSP_VBAT_AVDD_SEL=1)
Default = 7.8V (~2.7V) Nd = ((0.9×(N*16)/4095)-0⋅211764)x17) (V) (((0.9×(N*16)/4095)-0⋅225)x6 (V)) |
INT_MASK0 is shown in Table 7-170.
Return to the Summary Table.
Interrupt masks.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_MASK0 | R/W | 1b | Clock error interrupt mask.
0b = Don't Mask 1b = Mask |
6 | INT_MASK0 | R/W | 1b | PLL Lock interrupt mask.
0b = Don't Mask 1b = Mask |
5 | RESERVED | R/W | 1b | Reserved bit; Write only reset value |
4 | RESERVED | R/W | 1b | Reserved bit; Write only reset value |
3 | RESERVED | R/W | 1b | Reserved bit; Write only reset value |
2 | RESERVED | R/W | 1b | Reserved bit; Write only reset value |
1 | RESERVED | R/W | 1b | Reserved bit; Write only reset value |
0 | RESERVED | R/W | 1b | Reserved bit; Write only reset value |
INT_MASK4 is shown in Table 7-171.
Return to the Summary Table.
Interrupt masks.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
6 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
5 | INT_MASK4 | R/W | 0b | OUT Short Circuit Fault Interrupt Mask.
0b = Don't Mask 1b = Mask |
4 | INT_MASK4 | R/W | 0b | DRVR Virtual Ground Fault Interrupt Mask.
0b = Don't Mask 1b = Mask |
3 | INT_MASK4 | R/W | 0b | Headset insert detection interrupt mask.
0b = Don't Mask 1b = Mask |
2 | INT_MASK4 | R/W | 0b | Headset remove detection interrupt mask.
0b = Don't Mask 1b = Mask |
1 | INT_MASK4 | R/W | 0b | Headset detection hook(button) interrupt mask.
0b = Don't Mask 1b = Mask |
0 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
INT_MASK5 is shown in Table 7-172.
Return to the Summary Table.
Interrupt masks.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_MASK5 | R/W | 0b | GPA up threshold fault mask.
0b = Don't Mask 1b = Mask |
6 | INT_MASK5 | R/W | 0b | GPA low threshold fault mask.
0b = Don't Mask 1b = Mask |
5 | INT_MASK5 | R/W | 1b | VAD power up detect interrupt mask.
0b = Don't Mask 1b = Mask |
4 | INT_MASK5 | R/W | 1b | VAD power down detect interrupt mask.
0b = Don't Mask 1b = Mask |
3 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
2 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
1 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
0 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
INT_LTCH0 is shown in Table 7-173.
Return to the Summary Table.
Latched interrupt readback.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_LTCH0 | R | 0b | Interrupt due to clock error (self clearing bit).
0b = No interrupt 1b = Interrupt |
6 | INT_LTCH0 | R | 0b | Interrupt due to PLL Lock (self clearing bit)
0b = No interrupt 1b = Interrupt |
5 | RESERVED | R | 0b | Reserved bit; Write only reset value |
4 | RESERVED | R | 0b | Reserved bit; Write only reset value |
3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
2 | RESERVED | R | 0b | Reserved bit; Write only reset value |
1 | RESERVED | R | 0b | Reserved bit; Write only reset value |
0 | RESERVED | R | 0b | Reserved bit; Write only reset value |
CHx_LTCH is shown in Table 7-174.
Return to the Summary Table.
Channel level Diagnostics Latched Status
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | STS_CHx_LTCH | R | 0b | Status of Input CH1_LTCH.
0b = No faults occurred in input channel 1 1b = Fault or Faults have occurred in input channel 1 |
6 | STS_CHx_LTCH | R | 0b | Status of Input CH2_LTCH.
0b = No faults occurred in input channel 2 1b = Fault or Faults have occurred in input channel 2 |
5 | STS_CHx_LTCH | R | 0b | Status of Output CH1_LTCH.
0b = No faults occurred in output channel 1 1b = Fault or Faults have occurred in output channel 1 |
4 | STS_CHx_LTCH | R | 0b | Status of Output CH2_LTCH.
0b = No faults occurred in output channel 2 1b = Fault or Faults have occurred in output channel 2 |
3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
2 | RESERVED | R | 0b | Reserved bit; Write only reset value |
1 | RESERVED | R | 0b | Reserved bit; Write only reset value |
0 | RESERVED | R | 0b | Reserved bit; Write only reset value |
OUT_CH1_LTCH is shown in Table 7-175.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | OUT_CH1_LTCH | R | 0b | OUT1P Short Circuit Fault (self clearing bit).
0b = No short ciruit fault 1b = Short circuit fault |
6 | OUT_CH1_LTCH | R | 0b | OUT1M Short Circuit Fault (self clearing bit).
0b = No short ciruit fault 1b = Short circuit fault |
5 | OUT_CH1_LTCH | R | 0b | Channel 1 DRVRP Virtual Ground Fault (self clearing bit).
0b = No virtual ground fault 1b = Virtual ground fault |
4 | OUT_CH1_LTCH | R | 0b | Channel 1 DRVRM Virtual Ground Fault (self clearing bit).
0b = No virtual ground fault 1b = Virtual ground fault |
3 | MASK_ADC_CH1_OVRLD_FLAG | R/W | 0b | ADC CH1 OVRLD fault mask.
0b = Don't Mask 1b = Mask |
2 | MASK_ADC_CH2_OVRLD_FLAG | R/W | 0b | ADC CH2 OVRLD fault mask.
0b = Don't Mask 1b = Mask |
1-0 | RESERVED | R | 00b | Reserved bits; Write only reset value |
OUT_CH2_LTCH is shown in Table 7-176.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | OUT_CH2_LTCH | R | 0b | OUT2P Short Circuit Fault (self clearing bit).
0b = No short ciruit fault 1b = Short circuit fault |
6 | OUT_CH2_LTCH | R | 0b | OUT2M Short Circuit Fault (self clearing bit).
0b = No short ciruit fault 1b = Short circuit fault |
5 | OUT_CH2_LTCH | R | 0b | Channel 2 DRVRP Virtual Ground Fault (self clearing bit).
0b = No virtual ground fault 1b = Virtual ground fault |
4 | OUT_CH2_LTCH | R | 0b | Channel 2 DRVRM Virtual Ground Fault (self clearing bit).
0b = No virtual ground fault 1b = Virtual ground fault |
3-2 | RESERVED | R | 00b | Reserved bits; Write only reset value |
1 | MASK_AREG_SC_FLAG | R/W | 0b | AREG SC fault mask.
0b = Don't Mask 1b = Mask |
0 | AREG_SC_FLAG_LTCH | R | 0b | AREG SC fault (self clearing bit).
0b = No AREG short circuit fault 1b = AREG short ciruit fault |
INT_LTCH1 is shown in Table 7-177.
Return to the Summary Table.
Latched interrupt readback.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0b | Reserved bit; Write only reset value |
6 | RESERVED | R | 0b | Reserved bit; Write only reset value |
5 | RESERVED | R | 0b | Reserved bit; Write only reset value |
4 | RESERVED | R | 0b | Reserved bit; Write only reset value |
3 | INT_LTCH1 | R | 0b | Interrupt due to Headset Insert Detection (self clearing bit).
0b = No interrupt 1b = Interrupt |
2 | INT_LTCH1 | R | 0b | Interrupt due to Headset Remove Detection (self clearing bit).
0b = No interrupt 1b = Interrupt |
1 | INT_LTCH1 | R | 0b | Interrupt due to Headset hook(button) (self clearing bit).
0b = No interrupt 1b = Interrupt |
0 | RESERVED | R | 0b | Reserved bit; Write only reset value |
INT_LTCH2 is shown in Table 7-178.
Return to the Summary Table.
Latched interrupt readback.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_LTCH2 | R | 0b | Interrupt due to GPA up threshold fault (self clearing bit).
0b = No interrupt 1b = Interrupt |
6 | INT_LTCH2 | R | 0b | Interrupt due to GPA low threshold fault (self clearing bit)
0b = No interrupt 1b = Interrupt |
5 | INT_LTCH2 | R | 0b | Interrupt due to VAD power up detect (self clearing bit).
0b = No interrupt 1b = Interrupt |
4 | INT_LTCH2 | R | 0b | Interrupt due to VAD power down detect (self clearing bit).
0b = No interrupt 1b = Interrupt |
3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
2 | RESERVED | R | 0b | Reserved bit; Write only reset value |
1 | RESERVED | R | 0b | Reserved bit; Write only reset value |
0 | RESERVED | R | 0b | Reserved bit; Write only reset value |
INT_LIVE0 is shown in Table 7-179.
Return to the Summary Table.
Latched interrupt readback.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_LIVE0 | R | 0b | Interrupt due to clock error .
0b = No interrupt 1b = Interrupt |
6 | INT_LIVE0 | R | 0b | Interrupt due to PLL Lock
0b = No interrupt 1b = Interrupt |
5 | RESERVED | R | 0b | Reserved bit; Write only reset value |
4 | RESERVED | R | 0b | Reserved bit; Write only reset value |
3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
2 | RESERVED | R | 0b | Reserved bit; Write only reset value |
1 | RESERVED | R | 0b | Reserved bit; Write only reset value |
0 | RESERVED | R | 0b | Reserved bit; Write only reset value |
CHx_LIVE is shown in Table 7-180.
Return to the Summary Table.
Channel level Diagnostics Live Status
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | STS_CHx_LIVE | R | 0b | Status of Input CH1_LIVE.
0b = No faults occurred in input channel 1 1b = Fault or Faults have occurred in input channel 1 |
6 | STS_CHx_LIVE | R | 0b | Status of Input CH2_LIVE.
0b = No faults occurred in input channel 2 1b = Fault or Faults have occurred in input channel 2 |
5 | STS_CHx_LIVE | R | 0b | Status of Output CH1_LIVE.
0b = No faults occurred in output channel 1 1b = Fault or Faults have occurred in output channel 1 |
4 | STS_CHx_LIVE | R | 0b | Status of Output CH2_LIVE.
0b = No faults occurred in output channel 2 1b = Fault or Faults have occurred in output channel 2 |
3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
2 | RESERVED | R | 0b | Reserved bit; Write only reset value |
1 | RESERVED | R | 0b | Reserved bit; Write only reset value |
0 | RESERVED | R | 0b | Reserved bit; Write only reset value |
OUT_CH1_LIVE is shown in Table 7-181.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | OUT_CH1_LIVE | R | 0b | OUT1P Short Circuit Fault .
0b = No short ciruit fault 1b = Short circuit fault |
6 | OUT_CH1_LIVE | R | 0b | OUT1M Short Circuit Fault .
0b = No short ciruit fault 1b = Short circuit fault |
5 | OUT_CH1_LIVE | R | 0b | Channel 1 DRVRP Virtual Ground Fault .
0b = No virtual ground fault 1b = Virtual ground fault |
4 | OUT_CH1_LIVE | R | 0b | Channel 1 DRVRM Virtual Ground Fault .
0b = No virtual ground fault 1b = Virtual ground fault |
3-0 | RESERVED | R | 0000b | Reserved bits; Write only reset value |
OUT_CH2_LIVE is shown in Table 7-182.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | OUT_CH2_LIVE | R | 0b | OUT2P Short Circuit Fault .
0b = No short ciruit fault 1b = Short circuit fault |
6 | OUT_CH2_LIVE | R | 0b | OUT2M Short Circuit Fault .
0b = No short ciruit fault 1b = Short circuit fault |
5 | OUT_CH2_LIVE | R | 0b | Channel 2 DRVRP Virtual Ground Fault .
0b = No virtual ground fault 1b = Virtual ground fault |
4 | OUT_CH2_LIVE | R | 0b | Channel 2 DRVRM Virtual Ground Fault .
0b = No virtual ground fault 1b = Virtual ground fault |
3-1 | RESERVED | R | 000b | Reserved bits; Write only reset value |
0 | AREG_SC_FLAG_LIVE | R | 0b | AREG SC fault .
0b = No AREG short circuit fault 1b = AREG short ciruit fault |
INT_LIVE1 is shown in Table 7-183.
Return to the Summary Table.
Live interrupt readback.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0b | Reserved bit; Write only reset value |
6 | RESERVED | R | 0b | Reserved bit; Write only reset value |
5 | RESERVED | R | 0b | Reserved bit; Write only reset value |
4 | RESERVED | R | 0b | Reserved bit; Write only reset value |
3 | INT_LIVE1 | R | 0b | Interrupt due to Headset Insert Detection .
0b = No interrupt 1b = Interrupt |
2 | INT_LIVE1 | R | 0b | Interrupt due to Headset Remove Detection .
0b = No interrupt 1b = Interrupt |
2 | INT_LIVE1 | R | 0b | Interrupt due to Headset hook(button) .
0b = No interrupt 1b = Interrupt |
1 | RESERVED | R | 0b | Reserved bit; Write only reset value |
0 | RESERVED | R | 0b |
INT_LIVE2 is shown in Table 7-184.
Return to the Summary Table.
Live interrupt readback.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_LIVE2 | R | 0b | Interrupt due to GPA up threshold fault .
0b = No interrupt 1b = Interrupt |
6 | INT_LIVE2 | R | 0b | Interrupt due to GPA low threshold fault
0b = No interrupt 1b = Interrupt |
5 | INT_LIVE2 | R | 0b | Interrupt due to VAD power up detect .
0b = No interrupt 1b = Interrupt |
4 | INT_LIVE2 | R | 0b | Interrupt due to VAD power down detect .
0b = No interrupt 1b = Interrupt |
3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
2 | RESERVED | R | 0b | Reserved bit; Write only reset value |
1 | RESERVED | R | 0b | Reserved bit; Write only reset value |
0 | RESERVED | R | 0b | Reserved bit; Write only reset value |
DIAG_CFG8 is shown in Table 7-185.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | GPA_UP_THRS_FLT_THRES[7:0] | R/W | 10111010b | General Purpose Analog High Threshold
Default = ~ 2.6V nd = ((0.9×(N*16)/4095)-0⋅225)x6 (V) |
DIAG_CFG9 is shown in Table 7-186.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | GPA_LOW_THRS_FLT_THRES[7:0] | R/W | 01001011b | General Purpose Analog Low Threshold
Default = ~ 0.2V nd = ((0.9×(N*16)/4095)-0⋅225)x6 (V) |
DIAG_CFG14 is shown in Table 7-187.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0b | Reserved bit; Write only reset value |
6-5 | AVDD_FILT_SEL[1:0] | R/W | 10b | AVDD filter select
0d = 3.5MHz 1d = 200kHz 2d = 100kHz 3d = No filter |
4 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
3-2 | VBAT_FILT_SEL[1:0] | R/W | 10b | VBAT filter select
0d = 3.5MHz 1d = 200kHz 2d = 100kHz 3d = No filter |
1 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
0 | RESERVED | R/W | 0b | Reserved bit; Write only reset value |
DIAGDATA_CFG is shown in Table 7-188.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RESERVED | R/W | 0000b | Reserved bits; Write only reset values |
3 | IADC_DATA_IN_DIAG_REGS | R/W | 0b | IADC channel data in diagnostics channel data registers
0b= Disabled 1b= Enabled |
2 | HOLD_IADC_DATA | R/W | 0b | Hold IADC data update during register readback
0b= Data update is not held, Data register is continuously updated 1b= Data update is held, Data register readback can be done |
1 | OVRD_VBAT_TEMP_DATA | R/W | 0b | Override VBAT and TEMP data
0b= Override Disabled 1b= Override Enabled |
0 | HOLD_SAR_DATA | R/W | 0b | Hold SAR data update during register readback
0b= Data update is not held, Data register is continuously updated 1b= Data update is held, Data register readback can be done |
DIAG_MON_MSB_MBIAS is shown in Table 7-189.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_MBIAS[7:0] | R | 00000000b | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_MBIAS is shown in Table 7-190.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_MBIAS[3:0] | R | 0000b | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 0001b | Channel ID |
DIAG_MON_MSB_OUT1P is shown in Table 7-191.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_OUT_CH1P[7:0] | R | 00000000b | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_OUT1P is shown in Table 7-192.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_OUT_CH1P[3:0] | R | 0000b | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 0110b | Channel ID |
DIAG_MON_MSB_OUT1M is shown in Table 7-193.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_OUT_CH1N[7:0] | R | 00000000b | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_OUT1M is shown in Table 7-194.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_OUT_CH1N[3:0] | R | 0000b | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 0111b | Channel ID |
DIAG_MON_MSB_OUT2P is shown in Table 7-195.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_OUT_CH2P[7:0] | R | 00000000b | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_OUT2P is shown in Table 7-196.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_OUT_CH2P[3:0] | R | 0000b | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 1000b | Channel ID |
DIAG_MON_MSB_OUT2M is shown in Table 7-197.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_OUT_CH2N[7:0] | R | 00000000b | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_OUT2M is shown in Table 7-198.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_OUT_CH2N[3:0] | R | 0000b | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 1001b | Channel ID |
DIAG_MON_MSB_TEMP is shown in Table 7-199.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_TEMP[7:0] | R | 00000000b | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_TEMP is shown in Table 7-200.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_TEMP[3:0] | R | 0000b | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 1010b | Channel ID |
DIAG_MON_MSB_MBIAS_LOAD is shown in Table 7-201.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_MBIAS_LOAD[7:0] | R | 00000000b | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_MBIAS_LOAD is shown in Table 7-202.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_MBIAS_LOAD[3:0] | R | 0000b | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 1011b | Channel ID |
DIAG_MON_MSB_AVDD is shown in Table 7-203.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_AVDD[7:0] | R | 00000000b | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_AVDD is shown in Table 7-204.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_AVDD[3:0] | R | 0000b | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 1100b | Channel ID |
DIAG_MON_MSB_GPA is shown in Table 7-205.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_GPA[7:0] | R | 00000000b | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_GPA is shown in Table 7-206.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_GPA[3:0] | R | 0000b | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 1101b | Channel ID |