JAJST67 January   2024 TAC5112-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 6.12 Timing Requirements: PDM Digital Microphone Interface
    13. 6.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 6.14 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
      2. 7.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 7.3.3 Input Channel Configurations
      4. 7.3.4 Output Channel Configurations
      5. 7.3.5 Reference Voltage
      6. 7.3.6 Programmable Microphone Bias
      7. 7.3.7 Signal-Chain Processing
        1. 7.3.7.1 ADC Signal-Chain
          1. 7.3.7.1.1 Programmable Channel Gain and Digital Volume Control
          2. 7.3.7.1.2 Programmable Channel Gain Calibration
          3. 7.3.7.1.3 Programmable Channel Phase Calibration
          4. 7.3.7.1.4 Programmable Digital High-Pass Filter
          5. 7.3.7.1.5 Programmable Digital Biquad Filters
          6. 7.3.7.1.6 Programmable Channel Summer and Digital Mixer
          7. 7.3.7.1.7 Configurable Digital Decimation Filters
            1. 7.3.7.1.7.1 Linear Phase Filters
              1. 7.3.7.1.7.1.1 Sampling Rate: 16kHz or 14.7kHz
              2. 7.3.7.1.7.1.2 Sampling Rate: 24kHz or 22.05kHz
              3. 7.3.7.1.7.1.3 Sampling Rate: 32kHz or 29.4kHz
              4. 7.3.7.1.7.1.4 Sampling Rate: 48kHz or 44.1kHz
              5. 7.3.7.1.7.1.5 Sampling Rate: 96kHz or 88.2kHz
              6. 7.3.7.1.7.1.6 Sampling Rate: 384kHz or 352.8kHz
        2. 7.3.7.2 DAC Signal-Chain
          1. 7.3.7.2.1 Programmable Channel Gain and Digital Volume Control
          2. 7.3.7.2.2 Programmable Channel Gain Calibration
          3. 7.3.7.2.3 Programmable Digital High-Pass Filter
          4. 7.3.7.2.4 Programmable Digital Biquad Filters
          5. 7.3.7.2.5 Programmable Digital Mixer
          6. 7.3.7.2.6 Configurable Digital Interpolation Filters
            1. 7.3.7.2.6.1 Linear Phase Filters
              1. 7.3.7.2.6.1.1 Sampling Rate: 16kHz or 14.7kHz
              2. 7.3.7.2.6.1.2 Sampling Rate: 24kHz or 22.05kHz
              3. 7.3.7.2.6.1.3 Sampling Rate: 32kHz or 29.4kHz
              4. 7.3.7.2.6.1.4 Sampling Rate: 48kHz or 44.1kHz
              5. 7.3.7.2.6.1.5 Sampling Rate: 96kHz or 88.2kHz
              6. 7.3.7.2.6.1.6 Sampling Rate: 384kHz or 352.8kHz
      8. 7.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 7.4 Device Functional Modes
  9. 8 Register Maps
    1. 8.1 TAC5212 Registers
    2. 8.2 TAC5212 Registers
    3. 8.3 TAC5212 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
  11. 10Power Supply Recommendations
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.4 Output Channel Configurations

The device consists of two pairs of analog output pins (OUTxP and OUTxM) that can be configured as differential inputs or single-ended outputs for playback channels. The device supports simultaneous playback of up to four channels of single-ended output or up to two channel differential output using the high-performance multichannel DAC. Table 7-9 shows the input source selection for the playback channels.

Table 7-9 Input Source Selection for the Playback Channel
P0_R100_D[7:5] : OUT1x_SRC[2:0]OUT1P/OUT1M Source Selection
000 (default)Output driver disabled
001DAC signal chain
010Analog bypass signal chain
011Mixing of DAC and analog bypass signal chains
100OUT1P for DAC and OUT1M for analog bypass signal chain
101OUT1P for analog bypass and OUT1M for DAC signal chain.
11xReserved. Do not use this setting.

Similarly, the input source selection setting for output channel 2 can be configured using the OUT2x_SRC[2:0] (P0_R107_D[7:5]) register bits.

The TAC5112-Q1 supports up to 2-channel differential output, up to 2-channel pseudo-differential output, and up to 4-channel single-ended output. Each of the output channels can be independently configured for differential or single-ended output.

Table 7-10 shows the configuration modes for the output pins

Table 7-10 Output Pin Configuration for the Playback Channel
P0_R100_D[4:2] : OUT1x_CFG[2:0]OUT1P/OUT1M Pin Configuration
000 (default)OUT1P/OUT1M as a differential pair
001OUT1P and OUT1M as independent single-ended outputs
010Mono Single Ended output on OUT1P only
011Mono Single Ended output on OUT1M only
100Pseudo-differential output with OUT1P as signal and OUT1M as VCOM
101Pseudo differential output with OUT1P as signal, OUT1M as VCOM and OUT2M as VCOM sense.
110Pseudo differential output with OUT1M as signal and OUT1P as VCOM
111Reserved. Do not use this setting.

Similarly, the output pin configuration for output channel 2 can be done using the OUT2x_CFG[2:0] (P0_R107_D[4:2]) register bits.

The TAC5112-Q1 can support a variety of loads including headphone, lineout, and receiver amplifiers. Load drive configurations are available for each pin independently. OUT1P_DRIVE[1:0] (OUT1x_CFG[7:6]) configures the load drive capability for the OUT1P pin. OUT1M_DRIVE[1:0], OUT2P_DRIVE[1:0], OUT2M_DRIVE[1:0] are the output drive control for OUT1M, OUT2P and OUT2M respectively.