JAJSNO1 December   2023 TAC5112

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 6.12 Timing Requirements: PDM Digital Microphone Interface
    13. 6.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 6.14 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
      2. 7.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 7.3.3 Input Channel Configurations
      4. 7.3.4 Output Channel Configurations
      5. 7.3.5 Reference Voltage
      6. 7.3.6 Programmable Microphone Bias
      7. 7.3.7 Signal-Chain Processing
        1. 7.3.7.1 ADC Signal-Chain
          1. 7.3.7.1.1 Programmable Channel Gain and Digital Volume Control
          2. 7.3.7.1.2 Programmable Channel Gain Calibration
          3. 7.3.7.1.3 Programmable Channel Phase Calibration
          4. 7.3.7.1.4 Programmable Digital High-Pass Filter
          5. 7.3.7.1.5 Programmable Digital Biquad Filters
          6. 7.3.7.1.6 Programmable Channel Summer and Digital Mixer
          7. 7.3.7.1.7 Configurable Digital Decimation Filters
            1. 7.3.7.1.7.1 Linear Phase Filters
              1. 7.3.7.1.7.1.1 Sampling Rate: 16 kHz or 14.7 kHz
              2. 7.3.7.1.7.1.2 Sampling Rate: 24 kHz or 22.05 kHz
              3. 7.3.7.1.7.1.3 Sampling Rate: 32 kHz or 29.4 kHz
              4. 7.3.7.1.7.1.4 Sampling Rate: 48 kHz or 44.1 kHz
              5. 7.3.7.1.7.1.5 Sampling Rate: 96 kHz or 88.2 kHz
              6. 7.3.7.1.7.1.6 Sampling Rate: 384 kHz or 352.8 kHz
        2. 7.3.7.2 DAC Signal-Chain
          1. 7.3.7.2.1 Programmable Channel Gain and Digital Volume Control
          2. 7.3.7.2.2 Programmable Channel Gain Calibration
          3. 7.3.7.2.3 Programmable Digital High-Pass Filter
          4. 7.3.7.2.4 Programmable Digital Biquad Filters
          5. 7.3.7.2.5 Programmable Digital Mixer
          6. 7.3.7.2.6 Configurable Digital Interpolation Filters
            1. 7.3.7.2.6.1 Linear Phase Filters
              1. 7.3.7.2.6.1.1 Sampling Rate: 16 kHz or 14.7 kHz
              2. 7.3.7.2.6.1.2 Sampling Rate: 24 kHz or 22.05 kHz
              3. 7.3.7.2.6.1.3 Sampling Rate: 32 kHz or 29.4 kHz
              4. 7.3.7.2.6.1.4 Sampling Rate: 48 kHz or 44.1 kHz
              5. 7.3.7.2.6.1.5 Sampling Rate: 96 kHz or 88.2 kHz
              6. 7.3.7.2.6.1.6 Sampling Rate: 384 kHz or 352.8 kHz
      8. 7.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1 TAC5212 Registers
      2. 7.5.2 TAC5212 Registers
      3. 7.5.3 TAC5212 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
7.3.7.1.6 Programmable Channel Summer and Digital Mixer

For applications that require an even higher SNR than that supported for each channel, the device's digital summing mode can be used. In this mode, the digital record data are summed up across the channel with an equal weightage factor, which helps in reducing the effective record noise.

The device supports a fully programmable mixer feature that can mix the various input channels with their custom programmable scale factor to generate the final output channels. Figure 7-19 shows a block diagram that describes the mixer 1 operation to generate output channel 1. The programmable coefficients for the mixer operation are located in the section.

GUID-014EBA2A-1F30-4F74-9A49-A68A00CB9BB2-low.gifFigure 7-19 Programmable Digital Mixer Block Diagram

A similar mixer operation is performed by mixer 2, mixer 3, and mixer 4 to generate output channel 2, channel 3, and channel 4, respectively.