JAJSNO6 December 2023 TAC5142
ADVANCE INFORMATION
Digital audio data flows between the host processor and the TAC5142 on the digital audio serial interface (ASI), or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation, support for the I2S and LJF, and the pin-selectable controller-target configurability for bus clock lines.
The device supports an audio bus controller or target mode of operation using the hardware pin MD0. In target mode, FSYNC and BCLK work as input pins whereas in controller mode, FSYNC and BCLK work as output pins generated by the device. Table 8-1 shows the master and slave mode selection using the MD0 pin.
MD0 | CONTROLLER AND TARGET SELECTION |
---|---|
Short to Ground | Target I2S Mode |
Short to Ground with 4.7K Ohms | Target TDM Mode |
Short to AVDD | Controller I2S Mode |
Short to AVDD with 4.7K Ohms | Controller TDM Mode |
Short to AVDD with 22K Ohms | Target LJ Mode |
The word length for audio serial interface (ASI) in TAC5142 can be selected through MD1 and MD2 Pins in target mode of operation. In controller mode, fixed word length of 32 bits is supported. The TAC5142 also supports 1.8V AVDD operation in target mode with 32 bit word length. Table 8-2 shows the configuration table for setting word length and AVDD supply voltage
MD1 | MD2 | CONTROLLER AND TARGET SELECTION |
---|---|---|
Low | Low | Word
Length=32 AVDD=3.3V |
Low | High | Word
Length=32 AVDD=1.8V |
High | Low | Word
Length=24 AVDD=3.3V |
High | High | Word
Length=16 AVDD=3.3V |
The TAC5142 offers slot configuration for target TDM mode of operation. This can be selected through MD3 pin when MD0 is configured in target TDM mode. For options on MD3 in other modes of operation, refer to Digital High-Pass Filter. Table 8-3 shows the slots selected in Target TDM mode of operation based on MD3 pin.
MD3 | ADC SLOTS | DAC SLOTS |
---|---|---|
Low | ADC Data on Slot 0 and 1 | DAC Data on Slot 0 and 1 |
High | ADC Data on Slot 2 and 3 | DAC Data on Slot 2 and 3 |