The device has a smart auto-configuration block to generate all necessary internal clocks required for the ADC modulator and the digital filter engine used for signal processing. This configuration is done by monitoring the frequency of the FSYNC and BCLK signal on the audio buses.

The device supports the various data sample rates (of the FSYNC signal frequency) and the BCLK to FSYNC ratio to configure all clock dividers, including the PLL configuration, internally without host programming. Table 6-7and Table 6-8 list the supported FSYNC and BCLK frequencies.

The TAC5311-Q1 also supports non-audio sample rates beyond those listed in prior tables. Refer to Clocking Configuration of Device and Flexible Clocking For TAx5x1x Family application report for more details.

The TAC5311-Q1 sample rate can be configured using registers CLK_CFG0 (P0_R50) and CLK_CFG1 (P0_R51) for primary and secondary ASI respectively. CLK_DET_STS0 (P0_R62) and CLK_DET_STS1 (P0_R63) registers also capture the device auto detect result for the FSYNC frequency in auto detection mode for the primary and secondary ASI respectively. The registers CLK_DET_STS2 (P0_R64) and CLK_DET_STS3 (P0_R65) capture the BCLK to FSYNC ratio detected by the device in the auto detection mode for the selected ASI which is chosen to be the PLL reference through the CLK_SRC_SEL (P0_R52_D[3:1]) registers. If the device finds any unsupported combinations of FSYNC frequency and BCLK to FSYNC ratios, the device generates an ASI clock-error interrupt and shuts down various blocks of the device accordingly.

The TAC5311-Q1 also supports enabling channels while some ADC channels are already in operation. This requires a pre-configuration before power to describe maximum number of channels which can be enabled while in opeartion to ensure proper clock generation and use. This can be configured by using register DYN_PUPD_CFG (P0_R119). ADC_DYN_PUPD_EN (P0_R119_D[7]) bit can be used to enable ADC channels dynamic power up. Number of maximum channels supported for dynamic power-up and power-down can be configured using ADC_DYN_MAXCH_SEL (P0_R119_D[6]) bit.

The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the modulators and digital filter engine, as well as other control blocks. The device also supports an option to use BCLK, GPIO1, or the GPIxA pin (as CCLK) as the audio clock source without using the PLL to reduce power consumption. However, the ADC performance may degrade based on jitter from the external clock source, and some processing features may not be supported if the external audio clock source frequency is not high enough. Therefore, TI recommends using the PLL for high-performance applications. The various options for the PLL reference can be set through the CLK_SRC_SEL (P0_R52_D[3:1]) registers. More details and information on how to configure and use the device in low-power mode without using the PLL are discussed in the TAC5x1x-Q1 Power Consumption Matrix Across Various Usage Scenarios application report.

The device also supports an audio bus controller mode operation using the GPIOx or GPIxA pin (as CCLK) as the reference input clock source and supports various flexible options and a wide variety of system clocks. More details and information on controller mode configuration and operation are discussed in the Clocking Configuration of Device and Flexible Clocking For TAx5x1x Family application report.

The audio bus clock error detection and auto-detect feature automatically generates all internal clocks, but can be disabled using the IGNORE_CLK_ERR (P0_R4_D[6]) and CUSTOM_CLK_CFG (P0_R50_D[0]) register bits, respectively. In the system, this disable feature can be used to support custom clock frequencies that are not covered by the auto detect scheme. For such application use cases, care must be taken to ensure that the multiple clock dividers are all configured appropriately. TI recommends using the PPC3 GUI for device configuration settings; for more details see the TAC5212EVM-PDK Evaluation module user's guide and the PurePath™ console graphical development suite. The Clocking Configuration of Device and Flexible Clocking For TAx5x1x Family application report also covers various aspects of the custom clock configurations. Refer Clock Error Configuration, Detection, and Modes Supported in TAx5x1x Family application report for more details about the clock detection module of the device.

When the PLL is turned off, the digital volume control and other features using programmable coeffients like biquads, mixer, AGC etc., except the high pass filter (HPF) are not applicable.