The general SPI protocol allows full-duplex, synchronous, serial communication between a host processor (the controller) and peripheral devices. The SPI controller (in this case, the host processor) generates the synchronizing clock (driven on to SCLK) and initiates transmissions by taking the peripheral-select pin CSZ from high to low. The SPI peripheral devices (such as the TAC5311-Q1) depend on a controller device to start and synchronize transmissions. A transmission begins when initiated by an SPI controller. The byte from the SPI controller begins shifting in on the peripheral PICO pin under the control of the controller serial clock (driven onto SCLK). When the byte shifts in on the PICO pin, a byte shifts out on the POCI pin to the controller shift register.Table 6-60

mentions the pin assignment for SPI mode of control.

The TAC5311-Q1 supports a standard SPI control protocol with a clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0) and a clock phase setting of 1 (typical microprocessor SPI control bit CPHA = 1). The CSZ pin can remain low between transmissions; however, the device only interprets the first eight bits transmitted after the falling edge of CSZ as a command byte, and the next eight bits as a data byte only if writing to a register. The device is entirely controlled by registers. Reading and writing these registers is accomplished by an 8-bit command sent to the PICO pin prior to the data for that register. Table 6-61 shows the command structure. The first seven bits specify the address of the register that is being written or read, from 0 to 127 (decimal). The command word ends with an R/W bit, which specifies the direction of data flow on the serial bus.

In the case of a register write, set the R/W bit to 0. A second byte of data is sent to the PICO pin and contains the data to be written to the register. A register read is accomplished in a similar fashion. The 8-bit command word sends the 7-bit register address, followed by the R/W bit equal to 1 to signify a register read. The 8-bit register data is then clocked out of the device on the POCI pin during the second eight SCLK clocks in the frame. The device supports sequential SPI addressing for a multiple-byte data write/read transfer until the CSZ pin is pulled high. A multiple-byte data write or read transfer is identical to a single-byte data write or read transfer, respectively, until all data byte transfers complete. The host device must keep the CSZ pin low during all data byte transfers. Figure 6-93 shows the single-byte write transfer and Figure 6-94 shows the single-byte read transfer.

Figure 6-93 SPI Single-Byte Write Transfer

Figure 6-94 SPI Single-Byte Read Transfer