JAJSNP6 January 2024 TAC5312-Q1
ADVANCE INFORMATION
Table 7-104 lists the memory-mapped registers for the Page 1 registers. All register offset addresses not listed in Table 7-104 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Reset Value | Section |
---|---|---|---|---|
0x0 | PAGE_CFG | Device page register | 0x00 | Section 7.2.1 |
0x3 | DSP_CFG0 | 0x00 | Section 7.2.2 | |
0xD | CLK_CFG0 | 0x00 | Section 7.2.3 | |
0xE | CHANNEL_CFG1 | 0x00 | Section 7.2.4 | |
0xF | CHANNEL_CFG2 | 0x00 | Section 7.2.5 | |
0x17 | SRC_CFG0 | SRC configuration register 1 | 0x00 | Section 7.2.6 |
0x18 | SRC_CFG1 | SRC configuration register 2 | 0x00 | Section 7.2.7 |
0x19 | JACK_DET_CFG0 | JACK DET configuration register 0 | 0x00 | Section 7.2.8 |
0x1A | JACK_DET_CFG1 | JACK DET configuration register 1 | 0x00 | Section 7.2.9 |
0x1B | JACK_DET_CFG2 | JACK DET configuration register 2 | 0x00 | Section 7.2.10 |
0x1C | JACK_DET_CFG3 | JACK DET configuration register 3 | 0x00 | Section 7.2.11 |
0x1E | LPAD_CFG1 | LPAD | 0x20 | Section 7.2.12 |
0x1F | LPSG_CFG1 | LPSG | 0x80 | Section 7.2.13 |
0x20 | LPAD_LPSG_CFG1 | LPAD and LPSG common configuration register 1 | 0x00 | Section 7.2.14 |
0x23 | LIMITER_CFG | Limiter configuration register 2 | 0x00 | Section 7.2.15 |
0x24 | AGC_DRC_CFG | AGC_DRC configuration register 2 | 0x00 | Section 7.2.16 |
0x2B | PLIM_CFG0 | PLIM configuration register 0 | 0x00 | Section 7.2.17 |
0x2C | MIXER_CFG0 | MISC configuration register 0 | 0x00 | Section 7.2.18 |
0x2D | MISC_CFG0 | MISC configuration register 0 | 0x00 | Section 7.2.19 |
0x2E | BRWNOUT | 0xBF | Section 7.2.20 | |
0x2F | INT_MASK0 | Interrupt Mask Register-0 | 0xFF | Section 7.2.21 |
0x30 | INT_MASK1 | Interrupt Mask Register-1 | 0x0F | Section 7.2.22 |
0x31 | INT_MASK2 | Interrupt Mask Register-2 | 0x00 | Section 7.2.23 |
0x32 | INT_MASK4 | Interrupt Mask Register-3 | 0x00 | Section 7.2.24 |
0x33 | INT_MASK5 | Interrupt Mask Register-3 | 0x30 | Section 7.2.25 |
0x34 | INT_LTCH0 | Latched Interrupt Readback Register-0 | 0x00 | Section 7.2.26 |
0x35 | CHx_LTCH | Summary of Diagnostics | 0x00 | Section 7.2.27 |
0x36 | IN_CH1_LTCH | 0x00 | Section 7.2.28 | |
0x37 | IN_CH2_LTCH | 0x00 | Section 7.2.29 | |
0x38 | OUT_CH1_LTCH | 0x00 | Section 7.2.30 | |
0x39 | OUT_CH2_LTCH | 0x00 | Section 7.2.31 | |
0x3A | INT_LTCH1 | Latched Interrupt Readback Register-0 | 0x00 | Section 7.2.32 |
0x3B | INT_LTCH2 | Latched Interrupt Readback Register-3 | 0x00 | Section 7.2.33 |
0x3C | INT_LIVE0 | Live Interrupt Readback Register-0 | 0x00 | Section 7.2.34 |
0x3D | CHx_LIVE | Summary of Diagnostics | 0x00 | Section 7.2.35 |
0x3E | IN_CH1_LIVE | 0x00 | Section 7.2.36 | |
0x3F | IN_CH2_LIVE | 0x00 | Section 7.2.37 | |
0x40 | OUT_CH1_LIVE | 0x00 | Section 7.2.38 | |
0x41 | OUT_CH2_LIVE | 0x00 | Section 7.2.39 | |
0x42 | INT_LIVE1 | Latched Interrupt Readback Register-0 | 0x00 | Section 7.2.40 |
0x43 | INT_LIVE2 | Latched Interrupt Readback Register-3 | 0x00 | Section 7.2.41 |
0x46 | DIAG_CFG0 | 0x00 | Section 7.2.42 | |
0x47 | DIAG_CFG1 | 0x37 | Section 7.2.43 | |
0x48 | DIAG_CFG2 | 0x87 | Section 7.2.44 | |
0x4A | DIAG_CFG4 | 0xB8 | Section 7.2.45 | |
0x4B | DIAG_CFG5 | 0x00 | Section 7.2.46 | |
0x4C | DIAG_CFG6 | 0xA2 | Section 7.2.47 | |
0x4D | DIAG_CFG7 | 0x48 | Section 7.2.48 | |
0x4E | DIAG_CFG8 | 0xBA | Section 7.2.49 | |
0x4F | DIAG_CFG9 | 0x4B | Section 7.2.50 | |
0x50 | DIAG_CFG10 | 0x88 | Section 7.2.51 | |
0x51 | DIAG_CFG11 | 0x40 | Section 7.2.52 | |
0x52 | DIAG_CFG12 | 0x44 | Section 7.2.53 | |
0x53 | DIAG_CFG13 | 0x00 | Section 7.2.54 | |
0x54 | DIAG_CFG14 | 0x48 | Section 7.2.55 | |
0x56 | DIAG_MON_MSB_VBAT | 0x00 | Section 7.2.56 | |
0x57 | DIAG_MON_LSB_VBAT | 0x00 | Section 7.2.57 | |
0x58 | DIAG_MON_MSB_MBIAS | 0x00 | Section 7.2.58 | |
0x59 | DIAG_MON_LSB_MBIAS | 0x01 | Section 7.2.59 | |
0x5A | DIAG_MON_MSB_IN1P | 0x00 | Section 7.2.60 | |
0x5B | DIAG_MON_LSB_IN1P | 0x02 | Section 7.2.61 | |
0x5C | DIAG_MON_MSB_IN1M | 0x00 | Section 7.2.62 | |
0x5D | DIAG_MON_LSB_IN1M | 0x03 | Section 7.2.63 | |
0x5E | DIAG_MON_MSB_IN2P | 0x00 | Section 7.2.64 | |
0x5F | DIAG_MON_LSB_IN2P | 0x04 | Section 7.2.65 | |
0x60 | DIAG_MON_MSB_IN2M | 0x00 | Section 7.2.66 | |
0x61 | DIAG_MON_LSB_IN2M | 0x05 | Section 7.2.67 | |
0x62 | DIAG_MON_MSB_OUT1P | 0x00 | Section 7.2.68 | |
0x63 | DIAG_MON_LSB_OUT1P | 0x06 | Section 7.2.69 | |
0x64 | DIAG_MON_MSB_OUT1M | 0x00 | Section 7.2.70 | |
0x65 | DIAG_MON_LSB_OUT1M | 0x07 | Section 7.2.71 | |
0x66 | DIAG_MON_MSB_OUT2P | 0x00 | Section 7.2.72 | |
0x67 | DIAG_MON_LSB_OUT2P | 0x08 | Section 7.2.73 | |
0x68 | DIAG_MON_MSB_OUT2M | 0x00 | Section 7.2.74 | |
0x69 | DIAG_MON_LSB_OUT2M | 0x09 | Section 7.2.75 | |
0x6A | DIAG_MON_MSB_TEMP | 0x00 | Section 7.2.76 | |
0x6B | DIAG_MON_LSB_TEMP | 0x0A | Section 7.2.77 | |
0x6C | DIAG_MON_MSB_MBIAS_LOAD | 0x00 | Section 7.2.78 | |
0x6D | DIAG_MON_LSB_MBIAS_LOAD | 0x0B | Section 7.2.79 | |
0x6E | DIAG_MON_MSB_AVDD | 0x00 | Section 7.2.80 | |
0x6F | DIAG_MON_LSB_AVDD | 0x0C | Section 7.2.81 | |
0x70 | DIAG_MON_MSB_GPA | 0x00 | Section 7.2.82 | |
0x71 | DIAG_MON_LSB_GPA | 0x0D | Section 7.2.83 | |
0x72 | BOOST_CFG | 0x00 | Section 7.2.84 | |
0x73 | MICBIAS_CFG | 0xA0 | Section 7.2.85 |
PAGE_CFG is shown in Figure 7-103 and described in Table 7-105.
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The device memory map is divided into pages. This register sets the page.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PAGE[7:0] | |||||||
R/W-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | PAGE[7:0] | R/W | 0x0 | These bits set the device page.
0d = Page 0 1d = Page 1 2d to 254d = Page 2 to page 254 respectively 255d = Page 255 |
DSP_CFG0 is shown in Figure 7-104 and described in Table 7-106.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | DIS_DVOL_OTF_CHG | EN_BQ_OTF_CHG |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
6 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
5 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
4 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
3 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
2 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
1 | DIS_DVOL_OTF_CHG | R/W | 0x0 | Disable run-time changes to DVOL settings.
0d = Digital volume control changes supported while ADC is powered-on 1d = Digital volume control changes not supported while ADC is powered-on. This is useful for 384 kHz and higher sample rate if more than one channel processing is required. |
0 | EN_BQ_OTF_CHG | R/W | 0x0 | Enable run-time changes to Biquad settings.
0d = Disable on the fly biquad changes 1d = Enable on the fly biquad changes |
CLK_CFG0 is shown in Figure 7-105 and described in Table 7-107.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT_TGT_CFG_OVR_PASI | CNT_TGT_CFG_OVR_SASI | RESERVED | RESERVED | PASI_USE_INT_FSYNC | SASI_USE_INT_FSYNC | RESERVED | |
R/W-0b | R/W-0b | R-0b | R-00b | R/W-0b | R/W-0b | R-0b | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CNT_TGT_CFG_OVR_PASI | R/W | 0x0 | ASI controller target Config Override Register
0d = controller-target Config as per PASI_CNT_CFG bit. 1d = Override the standard behavior of the PASI_CNT_CFG. In this case the clock auto detect feature is not available. PASI_CNT_CFG = 0 : BCLK is input but FSYNC is output. PASI_CNT_CFG = 1 : BCLK is output but FSYNC in input. |
6 | CNT_TGT_CFG_OVR_SASI | R/W | 0x0 | ASI controller target Config Override Register
0d = controller-target Config as per SASI_CNT_CFG bit. 1d = Override the standard behavior of the SASI_CNT_CFG. In this case the clock auto detect feature is not available. SASI_CNT_CFG = 0 : BCLK is input but FSYNC is output. SASI_CNT_CFG = 1 : BCLK is output but FSYNC in input. |
5 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
4-3 | RESERVED | R | 0x0 | Reserved bits; Write only reset values |
2 | PASI_USE_INT_FSYNC | R/W | 0x0 | For Primary use internal FSYNC in controller mode configuration.
0d = Use external FSYNC 1d = Use internal FSYNC |
1 | SASI_USE_INT_FSYNC | R/W | 0x0 | For Secondary use internal FSYNC in controller mode configuration.
0d = Use external FSYNC 1d = Use internal FSYNC |
0 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
CHANNEL_CFG1 is shown in Figure 7-106 and described in Table 7-108.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FORCE_DYN_MODE_CUST_MAX_CH | DYN_MODE_CUST_MAX_CH[3:0] | RESERVED | |||||
R/W-0b | R/W-0000b | R-000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | FORCE_DYN_MODE_CUST_MAX_CH | R/W | 0x0 | ADC Force dynamic mode custom max channel
0d = In Dynamic, Max channel is based on ADC_DYN_MAXCH_SEL 1d = In Dynamic mode, max channel is custom as DYN_MODE_CUST_MAX_CH |
6-3 | DYN_MODE_CUST_MAX_CH[3:0] | R/W | 0x0 | ADC Dynamic mode custom max channel configuration
[3]->CH4_EN [2]->CH3_EN [1]->CH2_EN [0]->CH1_EN |
2-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset values |
CHANNEL_CFG2 is shown in Figure 7-107 and described in Table 7-109.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DAC_FORCE_DYN_MODE_CUST_MAX_CH | DAC_DYN_MODE_CUST_MAX_CH[3:0] | RESERVED | |||||
R/W-0b | R/W-0000b | R-000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DAC_FORCE_DYN_MODE_CUST_MAX_CH | R/W | 0x0 | DAC Force dynamic mode custom max channel
0d = In Dynamic, Max channel is based on DAC_DYN_MAXCH_SEL 1d = In Dynamic mode, max channel is custom as per DAC_DYN_MODE_CUST_MAX_CH |
6-3 | DAC_DYN_MODE_CUST_MAX_CH[3:0] | R/W | 0x0 | DAC Dynamic mode custom max channel configuration ([3]->CH4_EN, [2]->CH3_EN, [1]->CH2_EN, [0]->CH1_EN)
[3]->CH4_EN [2]->CH3_EN [1]->CH2_EN [0]->CH1_EN |
2-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset values |
SRC_CFG0 is shown in Figure 7-108 and described in Table 7-110.
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This register is configuration register 1 for SRC.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SRC_EN | DIS_AUTO_SRC_DET | RESERVED | |||||
R/W-0b | R/W-0b | R-000000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SRC_EN | R/W | 0x0 | SRC enable config
0b = SRC disable 1b = SRC enable |
6 | DIS_AUTO_SRC_DET | R/W | 0x0 | SRC auto detect config
0b = SRC auto detect enabled 1b = SRC auto detect disabled |
5-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
SRC_CFG1 is shown in Figure 7-109 and described in Table 7-111.
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This register is configuration register 2 for SRC.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAIN_FS_CUSTOM_CFG | MAIN_FS_SELECT_CFG | MAIN_AUX_RATIO_M_CUSTOM_CFG[2:0] | MAIN_AUX_RATIO_N_CUSTOM_CFG[2:0] | ||||
R/W-0b | R/W-0b | R/W-000b | R/W-000b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | MAIN_FS_CUSTOM_CFG | R/W | 0x0 | Main Fs custom config
0b = Main Fs is auto inferred 1b = Main Fs need to be selected from MAIN_FS_SELECT_CFG |
6 | MAIN_FS_SELECT_CFG | R/W | 0x0 | Main Fs select config
0b = PASI Fs shall be used as Main Fs 1b = SASI Fs shall be used as Main Fs |
5-3 | MAIN_AUX_RATIO_M_CUSTOM_CFG[2:0] | R/W | 0x0 | Main and Aux Fs Ratio m:n config
0d = m is auto inferred 1d = 1 2d = 2 3d = 3 4d = 4 5d = Reserved 6d = 6 7d = Reserved |
2-0 | MAIN_AUX_RATIO_N_CUSTOM_CFG[2:0] | R/W | 0x0 | Main and Aux Fs Ratio m:n config
0d = n is auto inferred 1d = 1 2d = 2 3d = 3 4d = 4 5d = Reserved 6d = 6 7d = Reserved |
JACK_DET_CFG0 is shown in Figure 7-110 and described in Table 7-112.
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This register is the JACK DET configuration register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JACK_DET_MONITOR_FREQ[1:0] | JACK_DET_PULSE_WIDTH | RESERVED | RESERVED | HPDET_CLOCK_SEL[1:0] | RESERVED | ||
R/W-00b | R/W-0b | R-0b | R-0b | R/W-00b | R-0b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | JACK_DET_MONITOR_FREQ[1:0] | R/W | 0x0 | Headset Detection Pulse Frequency
0d = 0.5 Hz 1d = 1 Hz 2d = 7.5 Hz 3d = 15 Hz |
5 | JACK_DET_PULSE_WIDTH | R/W | 0x0 | Detector Pulse High Width
0d = 4ms (MICBIAS PIN Cap = 1 uF) 1d = 32ms (MICBIAS PIN Cap = 10 uF) |
4 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
3 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
2-1 | HPDET_CLOCK_SEL[1:0] | R/W | 0x0 | Headphone Detection Clock Timeperiod Select
0d = 1ms 1d = 2ms 2d = 4ms 3d = Reserved |
0 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
JACK_DET_CFG1 is shown in Figure 7-111 and described in Table 7-113.
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This register is the JACK DET configuration register 1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | JACK_DET_COMP_CTRL2 | JACK_DET_COMP_CTRL3[1:0] | HPDET_COUPLING | HPDET_USE_2x_CURR | JACK_DET_EN | RESERVED | |
R-0b | R/W-0b | R/W-00b | R/W-0b | R/W-0b | R/W-0b | R-0b | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
6 | JACK_DET_COMP_CTRL2 | R/W | 0x0 | Hook Press Threshold Control in Fixed External Resistance case, controls the choice of Lowest Microphone impedance to be supported or Highest Hook button Impedance to be supported
0d = Minimum Microphone resistance supported, R_Mic = 800 Ωs and Max Hook button impedance supported, R_Hook = 320 Ωs for AC coupled Headphones R26<3> = 0 (else, when R26<3> = 1, R_hook = 150 Ωs) 1d = Max Hook button impedance supported, R_hook = 680 Ωs and Minimum Microphone resistance supported, R_Mic = 1350 Ωs for AC coupled Headphones R26<3> = 0 (else, when R26<3> = 1, R_Mic = 1750 Ωs) |
5-4 | JACK_DET_COMP_CTRL3[1:0] | R/W | 0x0 | Hook Pressed Jack Insertion support, valid only for External Resistor Type P0_R25_D4 = 0 else Don't care.
0d = supports minimum Hook button impedance of 150 Ωs for Hook Pressed Jack Insertion detection 1d = supports minimum Hook button impedance of 100 Ωs for Hook Pressed Jack Insertion detection 2d = supports minimum Hook button impedance of 50 Ωs for Hook Pressed Jack Insertion detection 3d = Reserved |
3 | HPDET_COUPLING | R/W | 0x0 | Headphone detect coupling
0d = AC coupled 1d = DC coupled |
2 | HPDET_USE_2x_CURR | R/W | 0x0 | Headset detect current sel config
0d = 2x current for headphone detection disabled 1d = 2x current for headphone detection enabled |
1 | JACK_DET_EN | R/W | 0x0 | Headset Detection Enable
0d = Headset Detection Disabled 1d = Headset Detection Enabled |
0 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
JACK_DET_CFG2 is shown in Figure 7-112 and described in Table 7-114.
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This register is the JACK DET configuration register 2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HPDET_DEB | JACK_DET_DEB_INSERT[2:0] | JACK_DET_DEB_REMOVAL | JACK_DET_DEB_HOOK_PRESS[1:0] | |||
R-0b | R/W-0b | R/W-000b | R/W-0b | R/W-00b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
6 | HPDET_DEB | R/W | 0x0 | Headphone Detection Debounce Programmability
0d = No Debounce 1d = Debounce of 3 detections |
5-3 | JACK_DET_DEB_INSERT[2:0] | R/W | 0x0 | Headset Insert Detection Debounce Programmability
0d = Debounce Time = 16ms 1d = Debounce Time = 32ms 2d = Debounce Time = 64ms 3d = Debounce Time = 128ms 4d = Debounce Time = 256ms 5d = Debounce Time = 512ms 6d = Reserved. Don not use 7d = No Debounce |
2 | JACK_DET_DEB_REMOVAL | R/W | 0x0 | Headset Removal Detection Debounce Programmability
0d = Debounce of 5 detections 1d = Debounce of 3 detections |
1-0 | JACK_DET_DEB_HOOK_PRESS[1:0] | R/W | 0x0 | Hook Press Debounce config
0d = No Debounce 1d = No Debounce 2d = Debounce of 2 detections 3d = Debounce of 3 detections |
JACK_DET_CFG3 is shown in Figure 7-113 and described in Table 7-115.
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This register is the JACK DET configuration register 3.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JACK_TYPE_FLAG[1:0] | HEADSET_TYPE_DET[1:0] | RESERVED | |||||
R-00b | R-00b | R-0000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | JACK_TYPE_FLAG[1:0] | R | 0x0 | Headset Jack type flag
0d = Jack is not inserted 1d = Jack is inserted without Microphone 2d = Reserved. Do not use 3d = Jack is inserted with Microphone |
5-4 | HEADSET_TYPE_DET[1:0] | R | 0x0 | Headset type
0d = Headset is not inserted 1d = Jack is inserted with mono-HS (RIGHT) 2d = Jack is inserted with mono-HS (LEFT) 3d = Jack is inserted with stereo-HS |
3-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
LPAD_CFG1 is shown in Figure 7-114 and described in Table 7-116.
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Low Power Activity Detection. Voice activity detection or Ultrasonic Activity detection configuration register 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LPAD_MODE[1:0] | LPAD_CH_SEL[1:0] | LPAD_SDOUT_INT_CFG | RESERVED | LPAD_PD_DET_EN | RESERVED | ||
R/W-00b | R/W-10b | R/W-0b | R-0b | R/W-0b | R-0b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | LPAD_MODE[1:0] | R/W | 0x0 | Auto ADC power up / power down configuration selection.
0d = User initiated ADC power-up and ADC power-down 1d = VAD/UAD interrupt based ADC power up and ADC power down 2d = VAD/UAD interrupt based ADC power up but user initiated ADC power down Dont use |
5-4 | LPAD_CH_SEL[1:0] | R/W | 0x2 | VAD channel select.
0d = Channel 1 is monitored for VAD/UAD activity 1d = Channel 2 is monitored for VAD/UAD activity 2d = Channel 3 is monitored for VAD/UAD activity 3d = Channel 4 is monitored for VAD/UAD activity |
3 | LPAD_SDOUT_INT_CFG | R/W | 0x0 | SDOUT interrupt configuration.
0d = SDOUT pin is not enabled for interrupt function 1d = SDOUT pin is enabled to support interrupt output when channel data in not being recorded |
2 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
1 | LPAD_PD_DET_EN | R/W | 0x0 | Enable ASI output data during VAD/UAD activity.
0d = VAD/UAD processing is not enabled during ADC recording 1d = VAD/UAD processing is enabled during ADC recording and VAD interrupts are generated as configured |
0 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
LPSG_CFG1 is shown in Figure 7-115 and described in Table 7-117.
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Low Power Signal Generation configuration register 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LPSG_CH_SEL[1:0] | RESERVED | RESERVED | |||||
R/W-10b | R-0b | R-00000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | LPSG_CH_SEL[1:0] | R/W | 0x2 | LPSG channel select.- UAG
0d = UAG activity is generated on channel 1 1d = UAG activity is generated on channel 2 2d = UAG activity is generated on channel 3 3d = UAG activity is generated on channel 4 |
5 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
4-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset values |
LPAD_LPSG_CFG1 is shown in Figure 7-116 and described in Table 7-118.
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This register is configuration register 1 for VAD/UAD/UAG.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LPAD_LPSG_CLK_CFG[1:0] | LPAD_LPSG_EXT_CLK_CFG[1:0] | RESERVED | LPAD_PH1_EN | RESERVED | |||
R/W-00b | R/W-00b | R-0b | R/W-0b | R-00b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | LPAD_LPSG_CLK_CFG[1:0] | R/W | 0x0 | Clock select for VAD/UAD/UAG
0d = VAD/UAD/UAG processing using internal oscillator clock 1d = VAD/UAD/UAG processing using external clock on BCLK input 2d = VAD/UAD/UAG processing using external clock on CCLK input 3d = Custom clock configuration based on CNT_CFG, CLK_SRC and CLKGEN_CFG registers in page 0 |
5-4 | LPAD_LPSG_EXT_CLK_CFG[1:0] | R/W | 0x0 | Clock configuration using external clock for VAD/UAD/UAG
0d = External clock is 24.576 MHz 1d = External clock is 6.144 MHz 2d = External clock is 12.288 MHz 3d = External clock is 18.432 MHz |
3 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
2 | LPAD_PH1_EN | R/W | 0x0 | Enable LPAD Phase 1 detection through Jack Detection comparator.
0d = LPAD phase 1 diabled 1d = LPAD phase 1 enabled |
1-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset values |
LIMITER_CFG is shown in Figure 7-117 and described in Table 7-119.
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This register is configuration register 2 for Limiter.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LIMITER_INP_SEL[1:0] | LIMITER_OUT_SEL[1:0] | RESERVED | |||||
R/W-00b | R/W-00b | R-0000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | LIMITER_INP_SEL[1:0] | R/W | 0x0 | Limiter input select config
0d = max(dacin_ch0, dacin_ch1) 1d = dacin_ch1 2d = dacin_ch0 3d = avg(dacin_ch0, dacin_ch1) |
5-4 | LIMITER_OUT_SEL[1:0] | R/W | 0x0 | Limiter output select config
0d = applied on both 1d = dacin_ch1 2d = dacin_ch0 3d = applied none |
3-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset values |
AGC_DRC_CFG is shown in Figure 7-118 and described in Table 7-120.
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This register is configuration register 2 for AGC_DRC.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AGC_CH1_EN | AGC_CH2_EN | AGC_CH3_EN | AGC_CH4_EN | DRC_CH1_EN | DRC_CH2_EN | DRC_CH3_EN | DRC_CH4_EN |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | AGC_CH1_EN | R/W | 0x0 | AGC Channel 1 enable config
0d = disable 1d = enable |
6 | AGC_CH2_EN | R/W | 0x0 | AGC Channel 2 enable config
0d = disable 1d = enable |
5 | AGC_CH3_EN | R/W | 0x0 | AGC Channel 3 enable config
0d = disable 1d = enable |
4 | AGC_CH4_EN | R/W | 0x0 | AGC Channel 4 enable config
0d = disable 1d = enable |
3 | DRC_CH1_EN | R/W | 0x0 | DRC Channel 1 enable config
0d = disable 1d = enable |
2 | DRC_CH2_EN | R/W | 0x0 | DRC Channel 2 enable config
0d = disable 1d = enable |
1 | DRC_CH3_EN | R/W | 0x0 | DRC Channel 3 enable config
0d = disable 1d = enable |
0 | DRC_CH4_EN | R/W | 0x0 | DRC Channel 4 enable config
0d = disable 1d = enable |
PLIM_CFG0 is shown in Figure 7-119 and described in Table 7-121.
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This register is configuration register 0 for PLIM.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_PLIM | PLIM_ATTN_VAL[2:0] | PLIM_BY_SAR_GPA | PLIM_RECOVERY | RESERVED | |||
R/W-0b | R/W-000b | R/W-0b | R/W-0b | R-00b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | EN_PLIM | R/W | 0x0 | Enable PLIM
0d = Disable 1d = Enable |
6-4 | PLIM_ATTN_VAL[2:0] | R/W | 0x0 | PLIM attenuation factor
0d = 0dB 1d = -6dB 2d = -12dB 3d = -18dB 4d = -24dB 5d = -30dB 6d = -36dB 7d = -42dB |
3 | PLIM_BY_SAR_GPA | R/W | 0x0 | PLIM attenuation value source
0d = Plimit attentation based on GPIO and reg_plimi_attn_val 1d = Plimit attenuation based on GPA Analog voltage. LUT will map SAR ADC data to Attenuation factor |
2 | PLIM_RECOVERY | R/W | 0x0 | PLIM attenuation recovery
0d = Plimit func doesn’t recover. It stays at same attenuation level or can apply more attenuation if required 1d = Plimit func recovers (reduces the attenuation) if “gpio_val=0” or “sar_adc_gpa” data suggest that Battery Voltage has recovered then we can reduce the attenuation being applied |
1-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
MIXER_CFG0 is shown in Figure 7-120 and described in Table 7-122.
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This register is the MISC configuration register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_DAC_ASI_MIXER | EN_SIDE_CHAIN_MIXER | EN_ADC_CHANNEL_MIXER | EN_LOOPBACK_MIXER | RESERVED | |||
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R-0000b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | EN_DAC_ASI_MIXER | R/W | 0x0 | Enable DAC ASI Mixer
0b = Disabled 1b = Enabled |
6 | EN_SIDE_CHAIN_MIXER | R/W | 0x0 | Enable Side Chain Mixer
0b = Disabled 1b = Enabled |
5 | EN_ADC_CHANNEL_MIXER | R/W | 0x0 | Enable ADC Channel Mixer
0b = Disabled 1b = Enabled |
4 | EN_LOOPBACK_MIXER | R/W | 0x0 | Enable Loopback Mixer
0b = Disabled 1b = Enabled |
3-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
MISC_CFG0 is shown in Figure 7-121 and described in Table 7-123.
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This register is the MISC configuration register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_DISTORTION | EN_BOP | EN_THERMAL_FOLDBACK | EN_DRC | DAC_SIGNAL_GENERATOR_1_ENABLE | DAC_SIGNAL_GENERATOR_2_ENABLE | DSP_VBAT_AVDD_SEL | BRWNOUT_EN |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | EN_DISTORTION | R/W | 0x0 | Distortion Limiter enable config
0b = Distortion Limiter disable 1b = Distortion Limiter enable |
6 | EN_BOP | R/W | 0x0 | BOP enable config
0b = BOP disable 1b = BOP enable |
5 | EN_THERMAL_FOLDBACK | R/W | 0x0 | Thermal Foldback enable config
0b = Thermal Foldback disable 1b = Thermal Foldback enable |
4 | EN_DRC | R/W | 0x0 | DRC enable config
0b = DRC disable 1b = DRC enable |
3 | DAC_SIGNAL_GENERATOR_1_ENABLE | R/W | 0x0 | DAC signal generator 1 enable config
0b = Signal generator disabled 1b = Signal generator enabled |
2 | DAC_SIGNAL_GENERATOR_2_ENABLE | R/W | 0x0 | DAC signal generator 2 enable config
0b = Signal generator disabled 1b = Signal generator enabled |
1 | DSP_VBAT_AVDD_SEL | R/W | 0x0 | SAR data source select for DSP Limiter, BOP, DRC
0b = SAR VBAT data to DSP 1b = SAR AVDD data to DSP |
0 | BRWNOUT_EN | R/W | 0x0 | Brownout enable config
0b = Brownout disable 1b = Brownout enable |
BRWNOUT is shown in Figure 7-122 and described in Table 7-124.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BRWNOUT_THRS[7:0] | |||||||
R/W-10111111b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | BRWNOUT_THRS[7:0] | R/W | 0xBF | Threshold for brownout shutdown (IF P1_R45_D1->DSP_VBAT_AVDD_SEL=1)
Default = 7.8V (~2.7V) Nd = ((0.9×(N*16)/4095)-0⋅211764)x17) (V) (((0.9×(N*16)/4095)-0⋅225)x6 (V)) |
INT_MASK0 is shown in Figure 7-123 and described in Table 7-125.
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Interrupt masks.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_MASK0 | INT_MASK0 | INT_MASK0 | INT_MASK0 | INT_MASK0 | RESERVED | RESERVED | RESERVED |
R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_MASK0 | R/W | 0x1 | Clock error interrupt mask.
0b = Don't Mask 1b = Mask |
6 | INT_MASK0 | R/W | 0x1 | PLL Lock interrupt mask.
0b = Don't Mask 1b = Mask |
5 | INT_MASK0 | R/W | 0x1 | Boost Over Temperature interrupt mask.
0b = Don't Mask 1b = Mask |
4 | INT_MASK0 | R/W | 0x1 | Boost Over Current interrupt mask.
0b = Don't Mask 1b = Mask |
3 | INT_MASK0 | R/W | 0x1 | Boost MO interrupt mask.
0b = Don't Mask 1b = Mask |
2 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
1 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
0 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
INT_MASK1 is shown in Figure 7-124 and described in Table 7-126.
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Interrupt masks.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_MASK1 | INT_MASK1 | INT_MASK1 | INT_MASK1 | INT_MASK1 | RESERVED | RESERVED | RESERVED |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-1b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_MASK1 | R/W | 0x0 | Channel-1 Input DC Faults Diagnostic Interrupt Mask.
0b = Don't Mask 1b = Mask |
6 | INT_MASK1 | R/W | 0x0 | Channel-2 Input DC Faults Diagnostic Interrupt Mask.
0b = Don't Mask 1b = Mask |
5 | INT_MASK1 | R/W | 0x0 | Channel-1 Output DC Faults Diagnostic Interrupt Mask.
0b = Don't Mask 1b = Mask |
4 | INT_MASK1 | R/W | 0x0 | Channel-2 Output DC Faults Diagnostic Interrupt Mask.
0b = Don't Mask 1b = Mask |
3 | INT_MASK1 | R/W | 0x1 | Input Faults Diagnostic Interrupt Mask for "Short to VBAT_IN" detect when VBAT_IN Voltage is less than MICBIAS Voltage.
0b = Don't Mask 1b = Mask |
2 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
1 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
0 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
INT_MASK2 is shown in Figure 7-125 and described in Table 7-127.
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Interrupt masks.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_MASK2 | INT_MASK2 | INT_MASK2 | INT_MASK2 | INT_MASK2 | INT_MASK2 | INT_MASK2 | INT_MASK2 |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_MASK2 | R/W | 0x0 | Input Diagnostics - Open Inputs Fault Interrupt Mask.
0b = Don't Mask 1b = Mask |
6 | INT_MASK2 | R/W | 0x0 | Input Diagnostics - Inputs Shorted Fault Interrupt Mask.
0b = Don't Mask 1b = Mask |
5 | INT_MASK2 | R/W | 0x0 | Input Diagnostics - INP Shorted to GND Fault Interrupt Mask.
0b = Don't Mask 1b = Mask |
4 | INT_MASK2 | R/W | 0x0 | Input Diagnostics - INM Shorted to GND Fault Interrupt Mask.
0b = Don't Mask 1b = Mask |
3 | INT_MASK2 | R/W | 0x0 | Input Diagnostics - INP Shorted to MICBIAS Fault Interrupt Mask.
0b = Don't Mask 1b = Mask |
2 | INT_MASK2 | R/W | 0x0 | Input Diagnostics - INM Shorted to MICBIAS Fault Interrupt Mask.
0b = Don't Mask 1b = Mask |
1 | INT_MASK2 | R/W | 0x0 | Input Diagnostics - INP Shorted to VBAT_IN Fault Interrupt Mask.
0b = Don't Mask 1b = Mask |
0 | INT_MASK2 | R/W | 0x0 | Input Diagnostics - INM Shorted to VBAT_IN Fault Interrupt Mask.
0b = Don't Mask 1b = Mask |
INT_MASK4 is shown in Figure 7-126 and described in Table 7-128.
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Interrupt masks.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_MASK4 | INT_MASK4 | INT_MASK4 | INT_MASK4 | INT_MASK4 | INT_MASK4 | INT_MASK4 | RESERVED |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_MASK4 | R/W | 0x0 | INP overvoltage fault mask.
0b = Don't Mask 1b = Mask |
6 | INT_MASK4 | R/W | 0x0 | INM overvoltage fault mask.
0b = Don't Mask 1b = Mask |
5 | INT_MASK4 | R/W | 0x0 | OUT Short Circuit Fault Interrupt Mask.
0b = Don't Mask 1b = Mask |
4 | INT_MASK4 | R/W | 0x0 | DRVR Virtual Ground Fault Interrupt Mask.
0b = Don't Mask 1b = Mask |
3 | INT_MASK4 | R/W | 0x0 | Headset insert detection interrupt mask.
0b = Don't Mask 1b = Mask |
2 | INT_MASK4 | R/W | 0x0 | Headset remove detection interrupt mask.
0b = Don't Mask 1b = Mask |
1 | INT_MASK4 | R/W | 0x0 | Headset detection hook(button) interrupt mask.
0b = Don't Mask 1b = Mask |
0 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
INT_MASK5 is shown in Figure 7-127 and described in Table 7-129.
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Interrupt masks.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_MASK5 | INT_MASK5 | INT_MASK5 | INT_MASK5 | INT_MASK5 | INT_MASK5 | INT_MASK5 | INT_MASK5 |
R/W-0b | R/W-0b | R/W-1b | R/W-1b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_MASK5 | R/W | 0x0 | GPA up threshold fault mask.
0b = Don't Mask 1b = Mask |
6 | INT_MASK5 | R/W | 0x0 | GPA low threshold fault mask.
0b = Don't Mask 1b = Mask |
5 | INT_MASK5 | R/W | 0x1 | VAD power up detect interrupt mask.
0b = Don't Mask 1b = Mask |
4 | INT_MASK5 | R/W | 0x1 | VAD power down detect interrupt mask.
0b = Don't Mask 1b = Mask |
3 | INT_MASK5 | R/W | 0x0 | Micbias short circuit fault mask.
0b = Don't Mask 1b = Mask |
2 | INT_MASK5 | R/W | 0x0 | Micbias High current fault mask.
0b = Don't Mask 1b = Mask |
1 | INT_MASK5 | R/W | 0x0 | Micbias Low current fault mask.
0b = Don't Mask 1b = Mask |
0 | INT_MASK5 | R/W | 0x0 | Micbias Over voltage fault mask.
0b = Don't Mask 1b = Mask |
INT_LTCH0 is shown in Figure 7-128 and described in Table 7-130.
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Latched interrupt readback.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_LTCH0 | INT_LTCH0 | INT_LTCH0 | INT_LTCH0 | INT_LTCH0 | RESERVED | RESERVED | RESERVED |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_LTCH0 | R | 0x0 | Interrupt due to clock error (self clearing bit).
0b = No interrupt 1b = Interrupt |
6 | INT_LTCH0 | R | 0x0 | Interrupt due to PLL Lock (self clearing bit)
0b = No interrupt 1b = Interrupt |
5 | INT_LTCH0 | R | 0x0 | Interrupt due to Boost Over Temperature (self clearing bit).
0b = No interrupt 1b = Interrupt |
4 | INT_LTCH0 | R | 0x0 | Interrupt due to Boost Over Current.(self clearing bit).
0b = No interrupt 1b = Interrupt |
3 | INT_LTCH0 | R | 0x0 | Interrupt due to Boost MO. (self clearing bit).
0b = No interrupt 1b = Interrupt |
2 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
1 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
0 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
CHx_LTCH is shown in Figure 7-129 and described in Table 7-131.
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Channel level Diagnostics Latched Status
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STS_CHx_LTCH | STS_CHx_LTCH | STS_CHx_LTCH | STS_CHx_LTCH | STS_CHx_LTCH | RESERVED | RESERVED | RESERVED |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | STS_CHx_LTCH | R | 0x0 | Status of Input CH1_LTCH.
0b = No faults occurred in input channel 1 1b = Fault or Faults have occurred in input channel 1 |
6 | STS_CHx_LTCH | R | 0x0 | Status of Input CH2_LTCH.
0b = No faults occurred in input channel 2 1b = Fault or Faults have occurred in input channel 2 |
5 | STS_CHx_LTCH | R | 0x0 | Status of Output CH1_LTCH.
0b = No faults occurred in output channel 1 1b = Fault or Faults have occurred in output channel 1 |
4 | STS_CHx_LTCH | R | 0x0 | Status of Output CH2_LTCH.
0b = No faults occurred in output channel 2 1b = Fault or Faults have occurred in output channel 2 |
3 | STS_CHx_LTCH | R | 0x0 | Status on fault due "Short to VBAT_IN fault detected when VBAT_IN is less than MICBIAS"
0b = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS did NOT occur in any channel 1b = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS has occurred in atleast one channel |
2 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
1 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
0 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
IN_CH1_LTCH is shown in Figure 7-130 and described in Table 7-132.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IN_CH1_LTCH | IN_CH1_LTCH | IN_CH1_LTCH | IN_CH1_LTCH | IN_CH1_LTCH | IN_CH1_LTCH | IN_CH1_LTCH | IN_CH1_LTCH |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | IN_CH1_LTCH | R | 0x0 | Input Channel-1 Open Inputs (self clearing bit).
0b = No Open Inputs 1b = Open Inputs |
6 | IN_CH1_LTCH | R | 0x0 | Input Channel-1 Inputs Shorted (self clearing bit).
0b = No Input Shorted 1b = Input Shorted each Other |
5 | IN_CH1_LTCH | R | 0x0 | Input Channel-1 INP Shorted to GND (self clearing bit).
0b = INP not shorted to GND 1b = INP shorted to GND |
4 | IN_CH1_LTCH | R | 0x0 | Input Channel-1 INM Shorted to GND (self clearing bit).
0b = INM not shorted to GND 1b = INM shorted to GND |
3 | IN_CH1_LTCH | R | 0x0 | Input Channel-1 INP Shorted to MICBIAS (self clearing bit).
0b = INP not shorted to MICBIAS 1b = INP shorted to MICBIAS |
2 | IN_CH1_LTCH | R | 0x0 | Input Channel-1 INM Shorted to MICBIAS (self clearing bit).
0b = INM not shorted to MICBIAS 1b = INM shorted to MICBIAS |
1 | IN_CH1_LTCH | R | 0x0 | Input Channel-1 INP Shorted to VBAT_IN (self clearing bit).
0b = INP not shorted to VBAT_IN 1b = INP shorted to VBAT_IN |
0 | IN_CH1_LTCH | R | 0x0 | Input Channel-1 INM Shorted to VBAT_IN (self clearing bit).
0b = INM not shorted to VBAT_IN 1b = INM shorted to VBAT_IN |
IN_CH2_LTCH is shown in Figure 7-131 and described in Table 7-133.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IN_CH2_LTCH | IN_CH2_LTCH | IN_CH2_LTCH | IN_CH2_LTCH | IN_CH2_LTCH | IN_CH2_LTCH | IN_CH2_LTCH | IN_CH2_LTCH |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | IN_CH2_LTCH | R | 0x0 | Input Channel-2 Open Inputs (self clearing bit).
0b = No Open Inputs 1b = Open Inputs |
6 | IN_CH2_LTCH | R | 0x0 | Input Channel-2 Inputs Shorted (self clearing bit).
0b = No Input Shorted 1b = Input Shorted each Other |
5 | IN_CH2_LTCH | R | 0x0 | Input Channel-2 INP Shorted to GND (self clearing bit).
0b = INP not shorted to GND 1b = INP shorted to GND |
4 | IN_CH2_LTCH | R | 0x0 | Input Channel-2 INM Shorted to GND (self clearing bit).
0b = INM not shorted to GND 1b = INM shorted to GND |
3 | IN_CH2_LTCH | R | 0x0 | Input Channel-2 INP Shorted to MICBIAS (self clearing bit).
0b = INP not shorted to MICBIAS 1b = INP shorted to MICBIAS |
2 | IN_CH2_LTCH | R | 0x0 | Input Channel-2 INM Shorted to MICBIAS (self clearing bit).
0b = INM not shorted to MICBIAS 1b = INM shorted to MICBIAS |
1 | IN_CH2_LTCH | R | 0x0 | Input Channel-2 INP Shorted to VBAT_IN (self clearing bit).
0b = INP not shorted to VBAT_IN 1b = INP shorted to VBAT_IN |
0 | IN_CH2_LTCH | R | 0x0 | Input Channel-2 INM Shorted to VBAT_IN (self clearing bit).
0b = INM not shorted to VBAT_IN 1b = INM shorted to VBAT_IN |
OUT_CH1_LTCH is shown in Figure 7-132 and described in Table 7-134.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OUT_CH1_LTCH | OUT_CH1_LTCH | OUT_CH1_LTCH | OUT_CH1_LTCH | MASK_ADC_CH1_OVRLD_FLAG | MASK_ADC_CH2_OVRLD_FLAG | RESERVED | |
R-0b | R-0b | R-0b | R-0b | R/W-0b | R/W-0b | R-00b | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | OUT_CH1_LTCH | R | 0x0 | OUT1P Short Circuit Fault (self clearing bit).
0b = No short ciruit fault 1b = Short circuit fault |
6 | OUT_CH1_LTCH | R | 0x0 | OUT1M Short Circuit Fault (self clearing bit).
0b = No short ciruit fault 1b = Short circuit fault |
5 | OUT_CH1_LTCH | R | 0x0 | Channel 1 DRVRP Virtual Ground Fault (self clearing bit).
0b = No virtual ground fault 1b = Virtual ground fault |
4 | OUT_CH1_LTCH | R | 0x0 | Channel 1 DRVRM Virtual Ground Fault (self clearing bit).
0b = No virtual ground fault 1b = Virtual ground fault |
3 | MASK_ADC_CH1_OVRLD_FLAG | R/W | 0x0 | ADC CH1 OVRLD fault mask.
0b = Don't Mask 1b = Mask |
2 | MASK_ADC_CH2_OVRLD_FLAG | R/W | 0x0 | ADC CH2 OVRLD fault mask.
0b = Don't Mask 1b = Mask |
1-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
OUT_CH2_LTCH is shown in Figure 7-133 and described in Table 7-135.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OUT_CH2_LTCH | OUT_CH2_LTCH | OUT_CH2_LTCH | OUT_CH2_LTCH | RESERVED | MASK_AREG_SC_FLAG | AREG_SC_FLAG_LTCH | |
R-0b | R-0b | R-0b | R-0b | R-00b | R/W-0b | R-0b | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | OUT_CH2_LTCH | R | 0x0 | OUT2P Short Circuit Fault (self clearing bit).
0b = No short ciruit fault 1b = Short circuit fault |
6 | OUT_CH2_LTCH | R | 0x0 | OUT2M Short Circuit Fault (self clearing bit).
0b = No short ciruit fault 1b = Short circuit fault |
5 | OUT_CH2_LTCH | R | 0x0 | Channel 2 DRVRP Virtual Ground Fault (self clearing bit).
0b = No virtual ground fault 1b = Virtual ground fault |
4 | OUT_CH2_LTCH | R | 0x0 | Channel 2 DRVRM Virtual Ground Fault (self clearing bit).
0b = No virtual ground fault 1b = Virtual ground fault |
3-2 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
1 | MASK_AREG_SC_FLAG | R/W | 0x0 | AREG SC fault mask.
0b = Don't Mask 1b = Mask |
0 | AREG_SC_FLAG_LTCH | R | 0x0 | AREG SC fault (self clearing bit).
0b = No AREG short circuit fault 1b = AREG short ciruit fault |
INT_LTCH1 is shown in Figure 7-134 and described in Table 7-136.
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Latched interrupt readback.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_LTCH1 | INT_LTCH1 | INT_LTCH1 | INT_LTCH1 | INT_LTCH1 | INT_LTCH1 | INT_LTCH1 | INT_LTCH1 |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_LTCH1 | R | 0x0 | Channel-1 INP Over Voltage (self clearing bit).
0b = No INP Over Voltage fault 1b = INP Over Voltage fault has occured |
6 | INT_LTCH1 | R | 0x0 | Channel-1 INM Over Voltage (self clearing bit).
0b = No INM Over Voltage fault 1b = INM Over Voltage fault has occured |
5 | INT_LTCH1 | R | 0x0 | Channel-2 INP Over Voltage (self clearing bit).
0b = No INP Over Voltage fault 1b = INP Over Voltage fault has occured |
4 | INT_LTCH1 | R | 0x0 | Channel-2 INM Over Voltage (self clearing bit).
0b = No INM Over Voltage fault 1b = INM Over Voltage fault has occured |
3 | INT_LTCH1 | R | 0x0 | Interrupt due to Headset Insert Detection (self clearing bit).
0b = No interrupt 1b = Interrupt |
2 | INT_LTCH1 | R | 0x0 | Interrupt due to Headset Remove Detection (self clearing bit).
0b = No interrupt 1b = Interrupt |
1 | INT_LTCH1 | R | 0x0 | Interrupt due to Headset hook(button) (self clearing bit).
0b = No interrupt 1b = Interrupt |
0 | INT_LTCH1 | R | 0x0 | Interrupt due to MIPS overload (self clearing bit)
0b = No interrupt 1b = Interrupt |
INT_LTCH2 is shown in Figure 7-135 and described in Table 7-137.
Return to the Summary Table.
Latched interrupt readback.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_LTCH2 | INT_LTCH2 | INT_LTCH2 | INT_LTCH2 | INT_LTCH2 | INT_LTCH2 | INT_LTCH2 | INT_LTCH2 |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_LTCH2 | R | 0x0 | Interrupt due to GPA up threshold fault (self clearing bit).
0b = No interrupt 1b = Interrupt |
6 | INT_LTCH2 | R | 0x0 | Interrupt due to GPA low threshold fault (self clearing bit)
0b = No interrupt 1b = Interrupt |
5 | INT_LTCH2 | R | 0x0 | Interrupt due to VAD power up detect (self clearing bit).
0b = No interrupt 1b = Interrupt |
4 | INT_LTCH2 | R | 0x0 | Interrupt due to VAD power down detect (self clearing bit).
0b = No interrupt 1b = Interrupt |
3 | INT_LTCH2 | R | 0x0 | Interrupt due to Micbias short circuit condition (self clearing bit)
0b = No interrupt 1b = Interrupt |
2 | INT_LTCH2 | R | 0x0 | Interrupt due to Micbias High current fault (self clearing bit).
0b = No interrupt 1b = Interrupt |
1 | INT_LTCH2 | R | 0x0 | Interrupt due to Micbias Low current fault (self clearing bit)
0b = No interrupt 1b = Interrupt |
0 | INT_LTCH2 | R | 0x0 | Interrupt due to Micbias Over voltage fault (self clearing bit).
0b = No interrupt 1b = Interrupt |
INT_LIVE0 is shown in Figure 7-136 and described in Table 7-138.
Return to the Summary Table.
Latched interrupt readback.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_LIVE0 | INT_LIVE0 | INT_LIVE0 | INT_LIVE0 | INT_LIVE0 | RESERVED | RESERVED | RESERVED |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_LIVE0 | R | 0x0 | Interrupt due to clock error .
0b = No interrupt 1b = Interrupt |
6 | INT_LIVE0 | R | 0x0 | Interrupt due to PLL Lock
0b = No interrupt 1b = Interrupt |
5 | INT_LIVE0 | R | 0x0 | Interrupt due to Boost Over Temperature .
0b = No interrupt 1b = Interrupt |
4 | INT_LIVE0 | R | 0x0 | Interrupt due to Boost Over Current..
0b = No interrupt 1b = Interrupt |
3 | INT_LIVE0 | R | 0x0 | Interrupt due to Boost MO. .
0b = No interrupt 1b = Interrupt |
2 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
1 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
0 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
CHx_LIVE is shown in Figure 7-137 and described in Table 7-139.
Return to the Summary Table.
Channel level Diagnostics Live Status
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STS_CHx_LIVE | STS_CHx_LIVE | STS_CHx_LIVE | STS_CHx_LIVE | STS_CHx_LIVE | RESERVED | RESERVED | RESERVED |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | STS_CHx_LIVE | R | 0x0 | Status of Input CH1_LIVE.
0b = No faults occurred in input channel 1 1b = Fault or Faults have occurred in input channel 1 |
6 | STS_CHx_LIVE | R | 0x0 | Status of Input CH2_LIVE.
0b = No faults occurred in input channel 2 1b = Fault or Faults have occurred in input channel 2 |
5 | STS_CHx_LIVE | R | 0x0 | Status of Output CH1_LIVE.
0b = No faults occurred in output channel 1 1b = Fault or Faults have occurred in output channel 1 |
4 | STS_CHx_LIVE | R | 0x0 | Status of Output CH2_LIVE.
0b = No faults occurred in output channel 2 1b = Fault or Faults have occurred in output channel 2 |
3 | STS_CHx_LIVE | R | 0x0 | Status on fault due "Short to VBAT_IN fault detected when VBAT_IN is less than MICBIAS"
0b = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS did NOT occur in any channel 1b = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS has occurred in atleast one channel |
2 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
1 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
0 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
IN_CH1_LIVE is shown in Figure 7-138 and described in Table 7-140.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IN_CH1_LIVE | IN_CH1_LIVE | IN_CH1_LIVE | IN_CH1_LIVE | IN_CH1_LIVE | IN_CH1_LIVE | IN_CH1_LIVE | IN_CH1_LIVE |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | IN_CH1_LIVE | R | 0x0 | Input Channel-1 Open Inputs .
0b = No Open Inputs 1b = Open Inputs |
6 | IN_CH1_LIVE | R | 0x0 | Input Channel-1 Inputs Shorted .
0b = No Input Shorted 1b = Input Shorted each Other |
5 | IN_CH1_LIVE | R | 0x0 | Input Channel-1 INP Shorted to GND .
0b = INP not shorted to GND 1b = INP shorted to GND |
4 | IN_CH1_LIVE | R | 0x0 | Input Channel-1 INM Shorted to GND .
0b = INM not shorted to GND 1b = INM shorted to GND |
3 | IN_CH1_LIVE | R | 0x0 | Input Channel-1 INP Shorted to MICBIAS .
0b = INP not shorted to MICBIAS 1b = INP shorted to MICBIAS |
2 | IN_CH1_LIVE | R | 0x0 | Input Channel-1 INM Shorted to MICBIAS .
0b = INM not shorted to MICBIAS 1b = INM shorted to MICBIAS |
1 | IN_CH1_LIVE | R | 0x0 | Input Channel-1 INP Shorted to VBAT_IN .
0b = INP not shorted to VBAT_IN 1b = INP shorted to VBAT_IN |
0 | IN_CH1_LIVE | R | 0x0 | Input Channel-1 INM Shorted to VBAT_IN .
0b = INM not shorted to VBAT_IN 1b = INM shorted to VBAT_IN |
IN_CH2_LIVE is shown in Figure 7-139 and described in Table 7-141.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IN_CH2_LIVE | IN_CH2_LIVE | IN_CH2_LIVE | IN_CH2_LIVE | IN_CH2_LIVE | IN_CH2_LIVE | IN_CH2_LIVE | IN_CH2_LIVE |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | IN_CH2_LIVE | R | 0x0 | Input Channel-2 Open Inputs .
0b = No Open Inputs 1b = Open Inputs |
6 | IN_CH2_LIVE | R | 0x0 | Input Channel-2 Inputs Shorted .
0b = No Input Shorted 1b = Input Shorted each Other |
5 | IN_CH2_LIVE | R | 0x0 | Input Channel-2 INP Shorted to GND .
0b = INP not shorted to GND 1b = INP shorted to GND |
4 | IN_CH2_LIVE | R | 0x0 | Input Channel-2 INM Shorted to GND .
0b = INM not shorted to GND 1b = INM shorted to GND |
3 | IN_CH2_LIVE | R | 0x0 | Input Channel-2 INP Shorted to MICBIAS .
0b = INP not shorted to MICBIAS 1b = INP shorted to MICBIAS |
2 | IN_CH2_LIVE | R | 0x0 | Input Channel-2 INM Shorted to MICBIAS .
0b = INM not shorted to MICBIAS 1b = INM shorted to MICBIAS |
1 | IN_CH2_LIVE | R | 0x0 | Input Channel-2 INP Shorted to VBAT_IN .
0b = INP not shorted to VBAT_IN 1b = INP shorted to VBAT_IN |
0 | IN_CH2_LIVE | R | 0x0 | Input Channel-2 INM Shorted to VBAT_IN .
0b = INM not shorted to VBAT_IN 1b = INM shorted to VBAT_IN |
OUT_CH1_LIVE is shown in Figure 7-140 and described in Table 7-142.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OUT_CH1_LIVE | OUT_CH1_LIVE | OUT_CH1_LIVE | OUT_CH1_LIVE | RESERVED | |||
R-0b | R-0b | R-0b | R-0b | R-0000b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | OUT_CH1_LIVE | R | 0x0 | OUT1P Short Circuit Fault .
0b = No short ciruit fault 1b = Short circuit fault |
6 | OUT_CH1_LIVE | R | 0x0 | OUT1M Short Circuit Fault .
0b = No short ciruit fault 1b = Short circuit fault |
5 | OUT_CH1_LIVE | R | 0x0 | Channel 1 DRVRP Virtual Ground Fault .
0b = No virtual ground fault 1b = Virtual ground fault |
4 | OUT_CH1_LIVE | R | 0x0 | Channel 1 DRVRM Virtual Ground Fault .
0b = No virtual ground fault 1b = Virtual ground fault |
3-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
OUT_CH2_LIVE is shown in Figure 7-141 and described in Table 7-143.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OUT_CH2_LIVE | OUT_CH2_LIVE | OUT_CH2_LIVE | OUT_CH2_LIVE | RESERVED | AREG_SC_FLAG_LIVE | ||
R-0b | R-0b | R-0b | R-0b | R-000b | R-0b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | OUT_CH2_LIVE | R | 0x0 | OUT2P Short Circuit Fault .
0b = No short ciruit fault 1b = Short circuit fault |
6 | OUT_CH2_LIVE | R | 0x0 | OUT2M Short Circuit Fault .
0b = No short ciruit fault 1b = Short circuit fault |
5 | OUT_CH2_LIVE | R | 0x0 | Channel 2 DRVRP Virtual Ground Fault .
0b = No virtual ground fault 1b = Virtual ground fault |
4 | OUT_CH2_LIVE | R | 0x0 | Channel 2 DRVRM Virtual Ground Fault .
0b = No virtual ground fault 1b = Virtual ground fault |
3-1 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
0 | AREG_SC_FLAG_LIVE | R | 0x0 | AREG SC fault .
0b = No AREG short circuit fault 1b = AREG short ciruit fault |
INT_LIVE1 is shown in Figure 7-142 and described in Table 7-144.
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Live interrupt readback.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_LIVE1 | INT_LIVE1 | INT_LIVE1 | INT_LIVE1 | INT_LIVE1 | INT_LIVE1 | INT_LIVE1 | RESERVED |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_LIVE1 | R | 0x0 | Channel-1 INP Over Voltage .
0b = No INP Over Voltage fault 1b = INP Over Voltage fault has occured |
6 | INT_LIVE1 | R | 0x0 | Channel-1 INM Over Voltage .
0b = No INM Over Voltage fault 1b = INM Over Voltage fault has occured |
5 | INT_LIVE1 | R | 0x0 | Channel-2 INP Over Voltage .
0b = No INP Over Voltage fault 1b = INP Over Voltage fault has occured |
4 | INT_LIVE1 | R | 0x0 | Channel-2 INM Over Voltage .
0b = No INM Over Voltage fault 1b = INM Over Voltage fault has occured |
3 | INT_LIVE1 | R | 0x0 | Interrupt due to Headset Insert Detection .
0b = No interrupt 1b = Interrupt |
2 | INT_LIVE1 | R | 0x0 | Interrupt due to Headset Remove Detection .
0b = No interrupt 1b = Interrupt |
2 | INT_LIVE1 | R | 0x0 | Interrupt due to Headset hook(button) .
0b = No interrupt 1b = Interrupt |
1 | INT_LIVE1 | R | 0x0 | Interrupt due to MIPS overload
0b = No interrupt 1b = Interrupt |
0 | RESERVED | R | 0x0 |
INT_LIVE2 is shown in Figure 7-143 and described in Table 7-145.
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Live interrupt readback.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_LIVE2 | INT_LIVE2 | INT_LIVE2 | INT_LIVE2 | INT_LIVE2 | INT_LIVE2 | INT_LIVE2 | INT_LIVE2 |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_LIVE2 | R | 0x0 | Interrupt due to GPA up threshold fault .
0b = No interrupt 1b = Interrupt |
6 | INT_LIVE2 | R | 0x0 | Interrupt due to GPA low threshold fault
0b = No interrupt 1b = Interrupt |
5 | INT_LIVE2 | R | 0x0 | Interrupt due to VAD power up detect .
0b = No interrupt 1b = Interrupt |
4 | INT_LIVE2 | R | 0x0 | Interrupt due to VAD power down detect .
0b = No interrupt 1b = Interrupt |
3 | INT_LIVE2 | R | 0x0 | Interrupt due to Micbias short circuit condition
0b = No interrupt 1b = Interrupt |
2 | INT_LIVE2 | R | 0x0 | Interrupt due to Micbias High current fault .
0b = No interrupt 1b = Interrupt |
1 | INT_LIVE2 | R | 0x0 | Interrupt due to Micbias Low current fault
0b = No interrupt 1b = Interrupt |
0 | INT_LIVE2 | R | 0x0 | Interrupt due to Micbias Over voltage fault .
0b = No interrupt 1b = Interrupt |
DIAG_CFG0 is shown in Figure 7-144 and described in Table 7-146.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IN_CH1_DIAG_EN | IN_CH2_DIAG_EN | INCL_SE_INM | INCL_AC_COUP | OUT1P_DIAG_EN | OUT1M_DIAG_EN | OUT2P_DIAG_EN | OUT2M_DIAG_EN |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | IN_CH1_DIAG_EN | R/W | 0x0 | Channel-1 Input (IN1P and IN1M) Scan for Diagnostics
0b = Diagnostic Disabled 1b = Diagnostic Enabled |
6 | IN_CH2_DIAG_EN | R/W | 0x0 | Channel-2 Input (IN2P and IN2M) Scan for Diagnostics
0b = Diagnostic Disabled 1b = Diagnostic Enabled |
5 | INCL_SE_INM | R/W | 0x0 | INxM pin Diagnostics Scan Selection for Single Ended Configuration
0b = INxM pins of single ended channels are excluded for diagnosis 1b = INxM pins of single ended channels are included for diagnosis |
4 | INCL_AC_COUP | R/W | 0x0 | AC coupled channels pins Scan Selection for Diagnostics
0b = INxP and INxM pins of AC coupled channels are excluded for diagnosis 1b = INxP and INxM pins of AC coupled channels are included for diagnosis |
3 | OUT1P_DIAG_EN | R/W | 0x0 | Channel-1 Output OUT1P Scan for Diagnostics
0b = Diagnostic Disabled 1b = Diagnostic Enabled |
2 | OUT1M_DIAG_EN | R/W | 0x0 | Channel-1 Output OUT1M Scan for Diagnostics
0b = Diagnostic Disabled 1b = Diagnostic Enabled |
1 | OUT2P_DIAG_EN | R/W | 0x0 | Channel-2 Output OUT2P Scan for Diagnostics
0b = Diagnostic Disabled 1b = Diagnostic Enabled |
0 | OUT2M_DIAG_EN | R/W | 0x0 | Channel-2 Output OUT2M Scan for Diagnostics
0b = Diagnostic Disabled 1b = Diagnostic Enabled |
DIAG_CFG1 is shown in Figure 7-145 and described in Table 7-147.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_SHT_TERM[3:0] | DIAG_SHT_VBAT_IN[3:0] | ||||||
R/W-0011b | R/W-0111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_SHT_TERM[3:0] | R/W | 0x3 | INxP and INxM Terminal Short Detect Threshold
0d = INxP and INxM Terminal Short Detect Threshold Value is 0 mV 1d = INxP and INxM Terminal Short Detect Threshold Value is 30 mV 2d = INxP and INxM Terminal Short Detect Threshold Value is 60 mV 10d to 13d = INxP and INxM Terminal Short Detect Threshold Value is as per configuration 14d = INxP and INxM Terminal Short Detect Threshold Value is 420 mV 15d = INxP and INxM Terminal Short Detect Threshold Value is 450 mV |
3-0 | DIAG_SHT_VBAT_IN[3:0] | R/W | 0x7 | Short to VBAT_IN Detect Threshold
0d = Short to VBAT_IN Detect Threshold Value is 0 mV 1d = Short to VBAT_IN Detect Threshold Value is 30 mV 2d = Short to VBAT_IN Detect Threshold Value is 60 mV 10d to 13d = Short to VBAT_IN Detect Threshold Value is as per configuration 14d = Short to VBAT_IN Detect Threshold Value is 420 mV 15d = Short to VBAT_IN Detect Threshold Value is 450 mV |
DIAG_CFG2 is shown in Figure 7-146 and described in Table 7-148.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_SHT_GND[3:0] | DIAG_SHT_MICBIAS[3:0] | ||||||
R/W-1000b | R/W-0111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_SHT_GND[3:0] | R/W | 0x8 | Short to GND Detect Threshold
0d = Short to GND Detect Threshold Value is 0 mV 1d = Short to GND Detect Threshold Value is 60 mV 2d = Short to GND Detect Threshold Value is 120 mV 10d to 13d = Short to GND Detect Threshold Value is as per configuration 14d = Short to GND Detect Threshold Value is 840 mV 15d = Short to GND Detect Threshold Value is 900 mV |
3-0 | DIAG_SHT_MICBIAS[3:0] | R/W | 0x7 | Short to MICBIAS Detect Threshold
0d = Short to MICBIAS Detect Threshold Value is 0 mV 1d = Short to MICBIAS Detect Threshold Value is 30 mV 2d = Short to MICBIAS Detect Threshold Value is 60 mV 10d to 13d = Short to MICBIAS Detect Threshold Value is as per configuration 14d = Short to MICBIAS Detect Threshold Value is 420 mV 15d = Short to MICBIAS Detect Threshold Value is 450 mV |
DIAG_CFG4 is shown in Figure 7-147 and described in Table 7-149.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | FAULT_DBNCE_SEL[1:0] | VSHORT_DBNCE | DIAG_2X_THRES | |||
R-00b | R-00b | R/W-10b | R/W-0b | R/W-0b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0x0 | Reserved bits; Write only reset values |
5-4 | RESERVED | R | 0x0 | Reserved bits; Write only reset values |
3-2 | FAULT_DBNCE_SEL[1:0] | R/W | 0x2 | Debounce conut for all the faults (except VBAT_IN short when VBAT_IN < MicBias)
0b = 16 counts for debounce to filter-out false faults detection 1b = 8 counts for debounce to filter-out false faults detection 2b = 4 counts for debounce to filter-out false faults detection 3b = No debounce count |
1 | VSHORT_DBNCE | R/W | 0x0 | VBAT_IN short debounce count
0b = 16 counts for debounce to filter-out false faults detection 1b = 8 counts for debounce to filter-out false faults detection |
0 | DIAG_2X_THRES | R/W | 0x0 | Diagostic thresholds range scale
0d = Thresholds same as configrued 1d = All the configruation thresholds gets scale by 2 times |
DIAG_CFG5 is shown in Figure 7-148 and described in Table 7-150.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MOV_AVG_CFG[1:0] | MOV_AVG_DIS_MBIAS_LOAD | MOV_AVG_DIS_TEMP_SENS | MOV_AVG_DIS_GPA | RESERVED | |||
R/W-00b | R/W-0b | R/W-0b | R/W-0b | R-000b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | DIAG_MOV_AVG_CFG[1:0] | R/W | 0x0 | Moving average configuration
0d = Moving average disabled 1d = Moving average enabled with 0.5 weightage for new and old data 2d = Moving average enabled with 0.75 weightage for old data and 0.25 weightage for new data 3d = Reserved |
5 | MOV_AVG_DIS_MBIAS_LOAD | R/W | 0x0 | Moving average configuration for MicBias Load channel
0b = Moving average is enabled for Micbias Load channel 1b = Moving average is disabled for Micbias Load channel |
4 | MOV_AVG_DIS_TEMP_SENS | R/W | 0x0 | Moving average configuration for Temp sense channel
0b = Moving average is enabled for Temp sense channel 1b = Moving average is disabled for Temp sense channel |
3 | MOV_AVG_DIS_GPA | R/W | 0x0 | Moving average configuration for GPA channel
0b = Moving average is enabled for GPA channel 1b = Moving average is disabled for GPA channel |
2-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset values |
DIAG_CFG6 is shown in Figure 7-149 and described in Table 7-151.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MBIAS_HIGH_CURR_THRS[7:0] | |||||||
R/W-10100010b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | MBIAS_HIGH_CURR_THRS[7:0] | R/W | 0xA2 | Threshold for Micbias High current fault diagnostics
Default = ~ 27mA Nd = ((0.9×(N*16)/4095)-0⋅2)x72.83237 (mA) |
DIAG_CFG7 is shown in Figure 7-150 and described in Table 7-152.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MBIAS_LOW_CURR_THRS[7:0] | |||||||
R/W-01001000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | MBIAS_LOW_CURR_THRS[7:0] | R/W | 0x48 | Threshold for Micbias Low current fault diagnostics
Default = ~ 4mA Nd = ((0.9×(N*16)/4095)-0⋅2)x72.83237 (mA) |
DIAG_CFG8 is shown in Figure 7-151 and described in Table 7-153.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPA_UP_THRS_FLT_THRES[7:0] | |||||||
R/W-10111010b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | GPA_UP_THRS_FLT_THRES[7:0] | R/W | 0xBA | General Purpose Analog High Threshold
Default = ~ 2.6V nd = ((0.9×(N*16)/4095)-0⋅225)x6 (V) |
DIAG_CFG9 is shown in Figure 7-152 and described in Table 7-154.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPA_LOW_THRS_FLT_THRES[7:0] | |||||||
R/W-01001011b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | GPA_LOW_THRS_FLT_THRES[7:0] | R/W | 0x4B | General Purpose Analog Low Threshold
Default = ~ 0.2V nd = ((0.9×(N*16)/4095)-0⋅225)x6 (V) |
DIAG_CFG10 is shown in Figure 7-153 and described in Table 7-155.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PD_MBIAS_SHRT_CKT_FLT | PD_MBIAS_HIGH_CURR_FLT | PD_MBIAS_LOW_CURR_FLT | PD_MBIAS_OV_FLT | PD_MBIAS_OT_FLT | MAN_RCV_PD_FLT_CHK | MBIAS_FLT_AUTO_REC_EN | MICBIAS_SHRT_CKT_DET_DIS |
R/W-1b | R/W-0b | R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PD_MBIAS_SHRT_CKT_FLT | R/W | 0x1 | Powerdown configuration of Micbias during Short Circuit fault
0b = No change when fault occurs 1b = Micbias is disabled when fault occurs |
6 | PD_MBIAS_HIGH_CURR_FLT | R/W | 0x0 | Powerdown configuration of Micbias during High current fault
0b = No change when fault occurs 1b = Micbias is disabled when fault occurs |
5 | PD_MBIAS_LOW_CURR_FLT | R/W | 0x0 | Powerdown configuration of Micbias during Low current fault
0b = No change when fault occurs 1b = Micbias is disabled when fault occurs |
4 | PD_MBIAS_OV_FLT | R/W | 0x0 | Powerdown configuration of Micbias during high voltage fault
0b = No change when fault occurs 1b = Micbias is disabled when fault occurs |
3 | PD_MBIAS_OT_FLT | R/W | 0x1 | Powerdown configuration of Micbias during over temperature fault
0b = No change when fault occurs 1b = Micbias is disabled when fault occurs |
2 | MAN_RCV_PD_FLT_CHK | R/W | 0x0 | Manual Recovery (self clear bit)
0b = No effect 1b = Recheck fault status and re-powerup channels if they do not have any faults |
1 | MBIAS_FLT_AUTO_REC_EN | R/W | 0x0 | Micbias PD on faults Auto-Recovery Enable
0d = Auto recovery from Micbias faults disabled 1d = Auto recovery enabled |
0 | MICBIAS_SHRT_CKT_DET_DIS | R/W | 0x0 | Micbias Short Circuit fault detect config
0b = enable 1b = disable |
DIAG_CFG11 is shown in Figure 7-154 and described in Table 7-156.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SAFEBAND_MBIAS_OV_FLT[2:0] | RESERVED | ||||||
R/W-010b | R-00000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | SAFEBAND_MBIAS_OV_FLT[2:0] | R/W | 0x2 | Safeband cfgn for Mbias over voltage fault's lower boundary
0 = No safeband 1 = 30mV safeband (1LSb at 9b lvl) 2 = 60mV safeband (2LSb at 9b lvl) 3-7 = N*30mV |
4-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset values |
DIAG_CFG12 is shown in Figure 7-155 and described in Table 7-157.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SAFEBAND_INx_MBIAS_FLT[2:0] | SAFEBAND_INx_OV_FLT[2:0] | RESERVED | |||||
R/W-010b | R/W-001b | R-00b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | SAFEBAND_INx_MBIAS_FLT[2:0] | R/W | 0x2 | Safeband cfgn for INx Short to Mbias fault's upper boundary
0 = No safeband 1 = 30mV safeband (1LSb at 9b lvl) 2 = 60mV safeband (2LSb at 9b lvl) 3-7 = N*30mV |
4-2 | SAFEBAND_INx_OV_FLT[2:0] | R/W | 0x1 | Safeband cfgn for INx Overvoltage fault's lower boundary
0 = No safeband 1 = 30mV safeband (1LSb at 9b lvl) 2-7 = N*30mV Dont use |
1-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset values |
DIAG_CFG13 is shown in Figure 7-156 and described in Table 7-158.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_FORCE_EN | DIAG_EN_MICBIAS_LOAD | DIAG_EN_MICBIAS | DIAG_EN_VBAT | DIAG_EN_TEMP_SENSE | DIAG_EN_AVDD | DIAG_EN_GPA | RESERVED |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DIAG_FORCE_EN | R/W | 0x0 | Configuration for auto/manual enable for diag vbat, micbias, micbias load, temp
0b = Auto enabled (auto enabled if atlease one of the input channel diagnostics is enabled in DIAG_CFG0) 1b = Manual en/disable based on DIAG_CFG13 Register |
6 | DIAG_EN_MICBIAS_LOAD | R/W | 0x0 | Micbias current/load channel enable for Diagnostics, valid if DIAG_FORCE_EN = 1
0b = Diagnostic Disabled 1b = Diagnostic Enabled |
5 | DIAG_EN_MICBIAS | R/W | 0x0 | Micbias channel enable for Diagnostics, valid if DIAG_FORCE_EN = 1
0b = Diagnostic Disabled 1b = Diagnostic Enabled |
4 | DIAG_EN_VBAT | R/W | 0x0 | VBAT channel enable for Diagnostics, valid if DIAG_FORCE_EN = 1
0b = Diagnostic Disabled 1b = Diagnostic Enabled |
3 | DIAG_EN_TEMP_SENSE | R/W | 0x0 | Temp sense channel enable for Diagnostics, valid if DIAG_FORCE_EN = 1
0b = Diagnostic Disabled 1b = Diagnostic Enabled |
2 | DIAG_EN_AVDD | R/W | 0x0 | AVDD channel enable for Diagnostics
0b = Diagnostic Disabled 1b = Diagnostic Enabled |
1 | DIAG_EN_GPA | R/W | 0x0 | GPA channel enable for Diagnostics
0b = Diagnostic Disabled 1b = Diagnostic Enabled |
0 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
DIAG_CFG14 is shown in Figure 7-157 and described in Table 7-159.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AVDD_FILT_SEL[1:0] | RESERVED | VBAT_FILT_SEL[1:0] | RESERVED | VBAT_SHRT_FLT | ||
R-0b | R/W-10b | R-0b | R/W-10b | R-0b | R/W-0b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
6-5 | AVDD_FILT_SEL[1:0] | R/W | 0x2 | AVDD filter select
0d = 3.5MHz 1d = 200kHz 2d = 100kHz 3d = No filter |
4 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
3-2 | VBAT_FILT_SEL[1:0] | R/W | 0x2 | VBAT filter select
0d = 3.5MHz 1d = 200kHz 2d = 100kHz 3d = No filter |
1 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
0 | VBAT_SHRT_FLT | R/W | 0x0 | Cfgn on INx short to VBAT
0 = INx Overvoltage and INx short to VBAT are separate 1 = INx Overvoltage and INx short to VBAT are Ord together as VBAT short fault |
DIAG_MON_MSB_VBAT is shown in Figure 7-158 and described in Table 7-160.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_VBAT[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_VBAT[7:0] | R | 0x0 | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_VBAT is shown in Figure 7-159 and described in Table 7-161.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_VBAT[3:0] | Channel[3:0] | ||||||
R-0000b | R-0000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_VBAT[3:0] | R | 0x0 | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 0x0 | Channel ID |
DIAG_MON_MSB_MBIAS is shown in Figure 7-160 and described in Table 7-162.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_MBIAS[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_MBIAS[7:0] | R | 0x0 | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_MBIAS is shown in Figure 7-161 and described in Table 7-163.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_MBIAS[3:0] | Channel[3:0] | ||||||
R-0000b | R-0001b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_MBIAS[3:0] | R | 0x0 | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 0x1 | Channel ID |
DIAG_MON_MSB_IN1P is shown in Figure 7-162 and described in Table 7-164.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_IN_CH1P[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_IN_CH1P[7:0] | R | 0x0 | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_IN1P is shown in Figure 7-163 and described in Table 7-165.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_IN_CH1P[3:0] | Channel[3:0] | ||||||
R-0000b | R-0010b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_IN_CH1P[3:0] | R | 0x0 | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 0x2 | Channel ID |
DIAG_MON_MSB_IN1M is shown in Figure 7-164 and described in Table 7-166.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_IN_CH1N[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_IN_CH1N[7:0] | R | 0x0 | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_IN1M is shown in Figure 7-165 and described in Table 7-167.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_IN_CH1N[3:0] | Channel[3:0] | ||||||
R-0000b | R-0011b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_IN_CH1N[3:0] | R | 0x0 | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 0x3 | Channel ID |
DIAG_MON_MSB_IN2P is shown in Figure 7-166 and described in Table 7-168.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_IN_CH2P[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_IN_CH2P[7:0] | R | 0x0 | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_IN2P is shown in Figure 7-167 and described in Table 7-169.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_IN_CH2P[3:0] | Channel[3:0] | ||||||
R-0000b | R-0100b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_IN_CH2P[3:0] | R | 0x0 | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 0x4 | Channel ID |
DIAG_MON_MSB_IN2M is shown in Figure 7-168 and described in Table 7-170.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_IN_CH2N[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_IN_CH2N[7:0] | R | 0x0 | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_IN2M is shown in Figure 7-169 and described in Table 7-171.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_IN_CH2N[3:0] | Channel[3:0] | ||||||
R-0000b | R-0101b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_IN_CH2N[3:0] | R | 0x0 | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 0x5 | Channel ID |
DIAG_MON_MSB_OUT1P is shown in Figure 7-170 and described in Table 7-172.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_OUT_CH1P[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_OUT_CH1P[7:0] | R | 0x0 | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_OUT1P is shown in Figure 7-171 and described in Table 7-173.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_OUT_CH1P[3:0] | Channel[3:0] | ||||||
R-0000b | R-0110b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_OUT_CH1P[3:0] | R | 0x0 | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 0x6 | Channel ID |
DIAG_MON_MSB_OUT1M is shown in Figure 7-172 and described in Table 7-174.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_OUT_CH1N[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_OUT_CH1N[7:0] | R | 0x0 | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_OUT1M is shown in Figure 7-173 and described in Table 7-175.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_OUT_CH1N[3:0] | Channel[3:0] | ||||||
R-0000b | R-0111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_OUT_CH1N[3:0] | R | 0x0 | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 0x7 | Channel ID |
DIAG_MON_MSB_OUT2P is shown in Figure 7-174 and described in Table 7-176.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_OUT_CH2P[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_OUT_CH2P[7:0] | R | 0x0 | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_OUT2P is shown in Figure 7-175 and described in Table 7-177.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_OUT_CH2P[3:0] | Channel[3:0] | ||||||
R-0000b | R-1000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_OUT_CH2P[3:0] | R | 0x0 | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 0x8 | Channel ID |
DIAG_MON_MSB_OUT2M is shown in Figure 7-176 and described in Table 7-178.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_OUT_CH2N[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_OUT_CH2N[7:0] | R | 0x0 | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_OUT2M is shown in Figure 7-177 and described in Table 7-179.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_OUT_CH2N[3:0] | Channel[3:0] | ||||||
R-0000b | R-1001b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_OUT_CH2N[3:0] | R | 0x0 | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 0x9 | Channel ID |
DIAG_MON_MSB_TEMP is shown in Figure 7-178 and described in Table 7-180.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_TEMP[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_TEMP[7:0] | R | 0x0 | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_TEMP is shown in Figure 7-179 and described in Table 7-181.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_TEMP[3:0] | Channel[3:0] | ||||||
R-0000b | R-1010b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_TEMP[3:0] | R | 0x0 | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 0xA | Channel ID |
DIAG_MON_MSB_MBIAS_LOAD is shown in Figure 7-180 and described in Table 7-182.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_MBIAS_LOAD[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_MBIAS_LOAD[7:0] | R | 0x0 | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_MBIAS_LOAD is shown in Figure 7-181 and described in Table 7-183.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_MBIAS_LOAD[3:0] | Channel[3:0] | ||||||
R-0000b | R-1011b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_MBIAS_LOAD[3:0] | R | 0x0 | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 0xB | Channel ID |
DIAG_MON_MSB_AVDD is shown in Figure 7-182 and described in Table 7-184.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_AVDD[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_AVDD[7:0] | R | 0x0 | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_AVDD is shown in Figure 7-183 and described in Table 7-185.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_AVDD[3:0] | Channel[3:0] | ||||||
R-0000b | R-1100b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_AVDD[3:0] | R | 0x0 | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 0xC | Channel ID |
DIAG_MON_MSB_GPA is shown in Figure 7-184 and described in Table 7-186.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_GPA[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_GPA[7:0] | R | 0x0 | Diagnostic SAR Monitor Data MSB Byte |
DIAG_MON_LSB_GPA is shown in Figure 7-185 and described in Table 7-187.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_GPA[3:0] | Channel[3:0] | ||||||
R-0000b | R-1101b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_GPA[3:0] | R | 0x0 | Diagnostic SAR Monitor Data LSB Nibble |
3-0 | Channel[3:0] | R | 0xD | Channel ID |
BOOST_CFG is shown in Figure 7-186 and described in Table 7-188.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BOOST_DIS | BOOST_OCPEN | BOOST_PDz_FLT | RESERVED | RESERVED | RESERVED | ||
R/W-0b | R/W-0b | R/W-0b | R-0b | R-0b | R-000b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | BOOST_DIS | R/W | 0x0 | Boost Enable/Disable
0d = Internal Boost enable 1d = Internal Boost disable/bypass |
6 | BOOST_OCPEN | R/W | 0x0 | Boost Over Current Protection Enable/Disable
0d = Boost OCP is enable 1d = Boost OCP is disable |
5 | BOOST_PDz_FLT | R/W | 0x0 | Boost PD cfgn
0d = Boost is powered down if Micbias is powered down due to faults 1d = Boost is NOT powered down if Micbias is powered down due to faults |
4 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
3 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
2-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset values |
MICBIAS_CFG is shown in Figure 7-187 and described in Table 7-189.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MBIAS_VAL[3:0] | RESERVED | ||||||
R/W-1010b | R-0000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | MBIAS_VAL[3:0] | R/W | 0xA | MicBias Value
0d = Microphone Bias output is bypassed to BSTOUT/HVDD 1d = Microphone Bias is set to 3.0 V 2d = Microphone Bias is set to 3.5 V 3d = Microphone Bias is set to 4.0 V 4d = Microphone Bias is set to 4.5 V 5d = Microphone Bias is set to 5 V 6d = Microphone Bias is set to 5.5 V 7d = Microphone Bias is set to 6 V 8d = Microphone Bias is set to 6.5 V 9d = Microphone Bias is set to 7 V 10d = Microphone Bias is set to 7.5 V 11d = Microphone Bias is set to 8 V 12d = Microphone Bias is set to 8.5 V 13d = Microphone Bias is set to 9 V 14d = Microphone Bias is set to 9.5 V 15d = Microphone Bias is set to 10 V |
3-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |