JAJSNP6 January 2024 TAC5312-Q1
ADVANCE INFORMATION
Table 7-190 lists the memory-mapped registers for the Page_3 registers. All register offset addresses not listed in Table 7-190 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Reset Value | Section |
---|---|---|---|---|
0x0 | PAGE_CFG | Device page register | 0x00 | Section 7.3.1 |
0x1A | SASI_CFG0 | Secondary ASI configuration register 0 | 0x30 | Section 7.3.2 |
0x1B | SASI_TX_CFG0 | SASI TX configuration register 0 | 0x00 | Section 7.3.3 |
0x1C | SASI_TX_CFG1 | SASI TX configuration register 1 | 0x00 | Section 7.3.4 |
0x1D | SASI_TX_CFG2 | SASI TX configuration register 2 | 0x00 | Section 7.3.5 |
0x1E | SASI_TX_CH1_CFG | SASI TX Channel 1 configuration register | 0x00 | Section 7.3.6 |
0x1F | SASI_TX_CH2_CFG | SASI TX Channel 2 configuration register | 0x01 | Section 7.3.7 |
0x20 | SASI_TX_CH3_CFG | SASI TX Channel 3 configuration register | 0x02 | Section 7.3.8 |
0x21 | SASI_TX_CH4_CFG | SASI TX Channel 4 configuration register | 0x03 | Section 7.3.9 |
0x22 | SASI_TX_CH5_CFG | SASI TX Channel 5 configuration register | 0x04 | Section 7.3.10 |
0x23 | SASI_TX_CH6_CFG | SASI TX Channel 6 configuration register | 0x05 | Section 7.3.11 |
0x24 | SASI_TX_CH7_CFG | SASI TX Channel 7 configuration register | 0x06 | Section 7.3.12 |
0x25 | SASI_TX_CH8_CFG | SASI TX Channel 8 configuration register | 0x07 | Section 7.3.13 |
0x26 | SASI_RX_CFG0 | SASI RX configuration register 0 | 0x00 | Section 7.3.14 |
0x27 | SASI_RX_CFG1 | SASI RX configuration register 1 | 0x00 | Section 7.3.15 |
0x28 | SASI_RX_CH1_CFG | SASI RX Channel 1 configuration register | 0x00 | Section 7.3.16 |
0x29 | SASI_RX_CH2_CFG | SASI RX Channel 2 configuration register | 0x01 | Section 7.3.17 |
0x2A | SASI_RX_CH3_CFG | SASI RX Channel 3 configuration register | 0x02 | Section 7.3.18 |
0x2B | SASI_RX_CH4_CFG | SASI RX Channel 4 configuration register | 0x03 | Section 7.3.19 |
0x2C | SASI_RX_CH5_CFG | SASI RX Channel 5 configuration register | 0x04 | Section 7.3.20 |
0x2D | SASI_RX_CH6_CFG | SASI RX Channel 6 configuration register | 0x05 | Section 7.3.21 |
0x2E | SASI_RX_CH7_CFG | SASI RX Channel 7 configuration register | 0x06 | Section 7.3.22 |
0x2F | SASI_RX_CH8_CFG | SASI RX Channel 8 configuration register | 0x07 | Section 7.3.23 |
0x32 | CLK_CFG12 | Clock configuration register 12 | 0x00 | Section 7.3.24 |
0x33 | CLK_CFG13 | 0x00 | Section 7.3.25 | |
0x34 | CLK_CFG14 | Clock configuration register 14 | 0x10 | Section 7.3.26 |
0x35 | CLK_CFG15 | Clock configuration register 15 | 0x01 | Section 7.3.27 |
0x36 | CLK_CFG16 | Clock configuration register 16 | 0x00 | Section 7.3.28 |
0x37 | CLK_CFG17 | Clock configuration register 17 | 0x00 | Section 7.3.29 |
0x38 | CLK_CFG18 | Clock configuration register 18 | 0x08 | Section 7.3.30 |
0x39 | CLK_CFG19 | Clock configuration register 19 | 0x20 | Section 7.3.31 |
0x3A | CLK_CFG20 | Clock configuration register 20 | 0x04 | Section 7.3.32 |
0x3B | CLK_CFG21 | Clock configuration register 21 | 0x00 | Section 7.3.33 |
0x3C | CLK_CFG22 | Clock configuration register 18 | 0x01 | Section 7.3.34 |
0x3D | CLK_CFG23 | Clock configuration register 18 | 0x01 | Section 7.3.35 |
0x3E | CLK_CFG24 | Clock configuration register 21 | 0x01 | Section 7.3.36 |
0x44 | CLK_CFG30 | 0x00 | Section 7.3.37 | |
0x45 | CLK_CFG31 | 0x00 | Section 7.3.38 | |
0x46 | CLKOUT_CFG1 | CLKOUT configuration register 1 | 0x00 | Section 7.3.39 |
0x47 | CLKOUT_CFG2 | CLKOUT configuration register 2 | 0x01 | Section 7.3.40 |
0x48 | BSTCLK_CFG1 | Boost clock configuration register 1 | 0x00 | Section 7.3.41 |
0x49 | SARCLK_CFG1 | SAR clock configuration register 1 | 0x00 | Section 7.3.42 |
0x5B | ADC_OVRLD_FLAG | 0x00 | Section 7.3.43 |
PAGE_CFG is shown in Figure 7-188 and described in Table 7-191.
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The device memory map is divided into pages. This register sets the page.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PAGE[7:0] | |||||||
R/W-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | PAGE[7:0] | R/W | 0x0 | These bits set the device page.
0d = Page 0 1d = Page 1 2d to 254d = Page 2 to page 254 respectively 255d = Page 255 |
SASI_CFG0 is shown in Figure 7-189 and described in Table 7-192.
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This register is the ASI configuration register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SASI_FORMAT[1:0] | SASI_WLEN[1:0] | SASI_FSYNC_POL | SASI_BCLK_POL | SASI_BUS_ERR | SASI_BUS_ERR_RCOV | ||
R/W-00b | R/W-11b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | SASI_FORMAT[1:0] | R/W | 0x0 | Secondary ASI protocol format.
0d = TDM mode 1d = I2S mode 2d = LJ (left-justified) mode 3d = Reserved; Don't use |
5-4 | SASI_WLEN[1:0] | R/W | 0x3 | Secondary ASI word or slot length.
0d = 16 bits (Recommended this setting to be used with 10-kΩ input impedance configuration) 1d = 20 bits 2d = 24 bits 3d = 32 bits |
3 | SASI_FSYNC_POL | R/W | 0x0 | ASI FSYNC polarity (for SASI protocol only).
0d = Default polarity as per standard protocol 1d = Inverted polarity with respect to standard protocol |
2 | SASI_BCLK_POL | R/W | 0x0 | ASI BCLK polarity (for SASI protocol only).
0d = Default polarity as per standard protocol 1d = Inverted polarity with respect to standard protocol |
1 | SASI_BUS_ERR | R/W | 0x0 | ASI bus error detection.
0d = Enable bus error detection 1d = Disable bus error detection |
0 | SASI_BUS_ERR_RCOV | R/W | 0x0 | ASI bus error auto resume.
0d = Enable auto resume after bus error recovery 1d = Disable auto resume after bus error recovery and remain powered down until host configures the device |
SASI_TX_CFG0 is shown in Figure 7-190 and described in Table 7-193.
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This register is the SASI TX configuration register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SASI_TX_EDGE | SASI_TX_FILL | SASI_TX_LSB | SASI_TX_KEEPER[1:0] | SASI_TX_USE_INT_FSYNC | SASI_TX_USE_INT_BCLK | SASI_TDM_PULSE_WIDTH | |
R/W-0b | R/W-0b | R/W-0b | R/W-00b | R/W-0b | R/W-0b | R/W-0b | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SASI_TX_EDGE | R/W | 0x0 | Secondary ASI data output (on the primary and secondary data pin) transmit edge.
0d = Default edge as per the protocol configuration setting in SASI_BCLK_POL 1d = Inverted following edge (half cycle delay) with respect to the default edge setting |
6 | SASI_TX_FILL | R/W | 0x0 | Secondary ASI data output (on the primary and secondary data pin) for any unused cycles
0d = Always transmit 0 for unused cycles 1d = Always use Hi-Z for unused cycles |
5 | SASI_TX_LSB | R/W | 0x0 | Secondary ASI data output (on the primary and secondary data pin) for LSB transmissions.
0d = Transmit the LSB for a full cycle 1d = Transmit the LSB for the first half cycle and Hi-Z for the second half cycle |
4-3 | SASI_TX_KEEPER[1:0] | R/W | 0x0 | Secondary ASI data output (on the primary and secondary data pin) bus keeper.
0d = Bus keeper is always disabled 1d = Bus keeper is always enabled 2d = Bus keeper is enabled during LSB transmissions only for one cycle 3d = Bus keeper is enabled during LSB transmissions only for one and half cycles |
2 | SASI_TX_USE_INT_FSYNC | R/W | 0x0 | Secondary ASI uses internal FSYNC for output data generation in controller mode configuration as applicable.
0d = Use external FSYNC for ASI protocol data generation 1d = Use internal FSYNC for ASI protocol data generation |
1 | SASI_TX_USE_INT_BCLK | R/W | 0x0 | Secondary ASI uses internal BCLK for output data generation in controller mode configuration.
0d = Use external BCLK for ASI protocol data generation 1d = Use internal BCLK for ASI protocol data generation |
0 | SASI_TDM_PULSE_WIDTH | R/W | 0x0 | Secondary ASI fsync pulse width in TDM format.
0d = Fsync pulse is 1 bclk period wide 1d = Fsync pulse is 2 bclk period wide |
SASI_TX_CFG1 is shown in Figure 7-191 and described in Table 7-194.
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This register is the SASI TX configuration register 1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SASI_TX_OFFSET[4:0] | ||||||
R-000b | R/W-00000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
4-0 | SASI_TX_OFFSET[4:0] | R/W | 0x0 | Secondary ASI output data MSB slot 0 offset (on the primary and secondary data pin).
0d = ASI data MSB location has no offset and is as per standard protocol 1d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of one BCLK cycle with respect to standard protocol 2d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of two BCLK cycles with respect to standard protocol 3d to 30d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset assigned as per configuration 31d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of 31 BCLK cycles with respect to standard protocol |
SASI_TX_CFG2 is shown in Figure 7-192 and described in Table 7-195.
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This register is the SASI TX configuration register 2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SASI_TX_CH8_SEL | SASI_TX_CH7_SEL | SASI_TX_CH6_SEL | SASI_TX_CH5_SEL | SASI_TX_CH4_SEL | SASI_TX_CH3_SEL | SASI_TX_CH2_SEL | SASI_TX_CH1_SEL |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SASI_TX_CH8_SEL | R/W | 0x0 | Secondary ASI output channel 8 select.
0d = Secondary ASI channel 8 output is on DOUT 1d = Secondary ASI channel 8 output is on DOUT2 |
6 | SASI_TX_CH7_SEL | R/W | 0x0 | Secondary ASI output channel 7 select.
0d = Secondary ASI channel 7 output is on DOUT 1d = Secondary ASI channel 7 output is on DOUT2 |
5 | SASI_TX_CH6_SEL | R/W | 0x0 | Secondary ASI output channel 6 select.
0d = Secondary ASI channel 6 output is on DOUT 1d = Secondary ASI channel 6 output is on DOUT2 |
4 | SASI_TX_CH5_SEL | R/W | 0x0 | Secondary ASI output channel 5 select.
0d = Secondary ASI channel 5 output is on DOUT 1d = Secondary ASI channel 5 output is on DOUT2 |
3 | SASI_TX_CH4_SEL | R/W | 0x0 | Secondary ASI output channel 4 select.
0d = Secondary ASI channel 4 output is on DOUT 1d = Secondary ASI channel 4 output is on DOUT2 |
2 | SASI_TX_CH3_SEL | R/W | 0x0 | Secondary ASI output channel 3 select.
0d = Secondary ASI channel 3 output is on DOUT 1d = Secondary ASI channel 3 output is on DOUT2 |
1 | SASI_TX_CH2_SEL | R/W | 0x0 | Secondary ASI output channel 2 select.
0d = Secondary ASI channel 2 output is on DOUT 1d = Secondary ASI channel 2 output is on DOUT2 |
0 | SASI_TX_CH1_SEL | R/W | 0x0 | Secondary ASI output channel 1 select.
0d = Secondary ASI channel 1 output is on DOUT 1d = Secondary ASI channel 1 output is on DOUT2 |
SASI_TX_CH1_CFG is shown in Figure 7-193 and described in Table 7-196.
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This register is the SASI TX Channel 1 configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SASI_TX_CH1_CFG | SASI_TX_CH1_SLOT_NUM[4:0] | |||||
R-00b | R/W-0b | R/W-00000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
5 | SASI_TX_CH1_CFG | R/W | 0x0 | Secondary ASI output channel 1 configuration.
0d = Secondary ASI channel 1 output is in a tri-state condition 1d = Secondary ASI channel 1 output corresponds to ADC Channel 1 data |
4-0 | SASI_TX_CH1_SLOT_NUM[4:0] | R/W | 0x0 | Secondary ASI output channel 1 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I2S, LJ is left slot 15 16d = TDM is slot 16 or I2S, LJ is right slot 0 17d = TDM is slot 17 or I2S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is right slot 15 |
SASI_TX_CH2_CFG is shown in Figure 7-194 and described in Table 7-197.
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This register is the SASI TX Channel 2 configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SASI_TX_CH2_CFG | SASI_TX_CH2_SLOT_NUM[4:0] | |||||
R-00b | R/W-0b | R/W-00001b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
5 | SASI_TX_CH2_CFG | R/W | 0x0 | Secondary ASI output channel 2 configuration.
0d = Secondary ASI channel 2 output is in a tri-state condition 1d = Secondary ASI channel 2 output corresponds to ADC Channel 2 data |
4-0 | SASI_TX_CH2_SLOT_NUM[4:0] | R/W | 0x1 | Secondary ASI output channel 2 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I2S, LJ is left slot 15 16d = TDM is slot 16 or I2S, LJ is right slot 0 17d = TDM is slot 17 or I2S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is right slot 15 |
SASI_TX_CH3_CFG is shown in Figure 7-195 and described in Table 7-198.
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This register is the SASI TX Channel 3 configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SASI_TX_CH3_CFG[1:0] | SASI_TX_CH3_SLOT_NUM[4:0] | |||||
R-0b | R/W-00b | R/W-00010b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
6-5 | SASI_TX_CH3_CFG[1:0] | R/W | 0x0 | Secondary ASI output channel 3 configuration.
0d = Secondary ASI channel 3 output is in a tri-state condition 1d = Secondary ASI channel 3 output corresponds to ADC Channel 3 data 2d = Secondary ASI channel 3 output corresponds to VBAT data 3d = Reserved |
4-0 | SASI_TX_CH3_SLOT_NUM[4:0] | R/W | 0x2 | Secondary ASI output channel 3 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I2S, LJ is left slot 15 16d = TDM is slot 16 or I2S, LJ is right slot 0 17d = TDM is slot 17 or I2S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is right slot 15 |
SASI_TX_CH4_CFG is shown in Figure 7-196 and described in Table 7-199.
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This register is the SASI TX Channel 4 configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SASI_TX_CH4_CFG[1:0] | SASI_TX_CH4_SLOT_NUM[4:0] | |||||
R-0b | R/W-00b | R/W-00011b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
6-5 | SASI_TX_CH4_CFG[1:0] | R/W | 0x0 | Secondary ASI output channel 4 configuration.
0d = Secondary ASI channel 4 output is in a tri-state condition 1d = Secondary ASI channel 4 output corresponds to ADC Channel 4 data 2d = Secondary ASI channel 4 output corresponds to TEMP data 3d = Reserved |
4-0 | SASI_TX_CH4_SLOT_NUM[4:0] | R/W | 0x3 | Secondary ASI output channel 4 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I2S, LJ is left slot 15 16d = TDM is slot 16 or I2S, LJ is right slot 0 17d = TDM is slot 17 or I2S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is right slot 15 |
SASI_TX_CH5_CFG is shown in Figure 7-197 and described in Table 7-200.
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This register is the SASI TX Channel 5 configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SASI_TX_CH5_CFG[1:0] | SASI_TX_CH5_SLOT_NUM[4:0] | |||||
R-0b | R/W-00b | R/W-00100b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
6-5 | SASI_TX_CH5_CFG[1:0] | R/W | 0x0 | Secondary ASI output channel 5 configuration.
0d = Secondary ASI channel 5 output is in a tri-state condition 1d = Secondary ASI channel 5 output corresponds to ASI Input Channel 1 loopback data 2d = Secondary ASI channel 5 output corresponds to echo reference channel 1 data 3d = Reserved |
4-0 | SASI_TX_CH5_SLOT_NUM[4:0] | R/W | 0x4 | Secondary ASI output channel 5 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I2S, LJ is left slot 15 16d = TDM is slot 16 or I2S, LJ is right slot 0 17d = TDM is slot 17 or I2S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is right slot 15 |
SASI_TX_CH6_CFG is shown in Figure 7-198 and described in Table 7-201.
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This register is the SASI TX Channel 6 configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SASI_TX_CH6_CFG[1:0] | SASI_TX_CH6_SLOT_NUM[4:0] | |||||
R-0b | R/W-00b | R/W-00101b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
6-5 | SASI_TX_CH6_CFG[1:0] | R/W | 0x0 | Secondary ASI output channel 6 configuration.
0d = Secondary ASI channel 6 output is in a tri-state condition 1d = Secondary ASI channel 6 output corresponds to ASI Input Channel 2 loopback data 2d = Secondary ASI channel 6 output corresponds to echo reference channel 2 data 3d = Reserved |
4-0 | SASI_TX_CH6_SLOT_NUM[4:0] | R/W | 0x5 | Secondary ASI output channel 6 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I2S, LJ is left slot 15 16d = TDM is slot 16 or I2S, LJ is right slot 0 17d = TDM is slot 17 or I2S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is right slot 15 |
SASI_TX_CH7_CFG is shown in Figure 7-199 and described in Table 7-202.
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This register is the SASI TX Channel 7 configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SASI_TX_CH7_CFG[1:0] | SASI_TX_CH7_SLOT_NUM[4:0] | |||||
R-0b | R/W-00b | R/W-00110b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
6-5 | SASI_TX_CH7_CFG[1:0] | R/W | 0x0 | Secondary ASI output channel 7 configuration.
0d = Secondary ASI channel 7 output is in a tri-state condition 1d = Secondary ASI channel 7 output corresponds to {VBAT_WLby2, TEMP_WLby2} 2d = Secondary ASI channel 7 output corresponds to {echo_ref_ch1_wlby2, echo_ref_ch2_wlby2} 3d = Reserved |
4-0 | SASI_TX_CH7_SLOT_NUM[4:0] | R/W | 0x6 | Secondary ASI output channel 7 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I2S, LJ is left slot 15 16d = TDM is slot 16 or I2S, LJ is right slot 0 17d = TDM is slot 17 or I2S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is right slot 15 |
SASI_TX_CH8_CFG is shown in Figure 7-200 and described in Table 7-203.
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This register is the SASI TX Channel 8 configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SASI_TX_CH8_CFG | SASI_TX_CH8_SLOT_NUM[4:0] | |||||
R-00b | R/W-0b | R/W-00111b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
5 | SASI_TX_CH8_CFG | R/W | 0x0 | Secondary ASI output channel 8 configuration.
0d = Secondary ASI channel 8 output is in a tri-state condition 1d = Secondary ASI channel 8 output corresponds to ICLA data |
4-0 | SASI_TX_CH8_SLOT_NUM[4:0] | R/W | 0x7 | Secondary ASI output channel 8 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I2S, LJ is left slot 15 16d = TDM is slot 16 or I2S, LJ is right slot 0 17d = TDM is slot 17 or I2S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is right slot 15 |
SASI_RX_CFG0 is shown in Figure 7-201 and described in Table 7-204.
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This register is the SASI RX configuration register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SASI_RX_EDGE | SASI_RX_USE_INT_FSYNC | SASI_RX_USE_INT_BCLK | SASI_RX_OFFSET[4:0] | ||||
R/W-0b | R/W-0b | R/W-0b | R/W-00000b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SASI_RX_EDGE | R/W | 0x0 | Secondary ASI data input (on the primary and secondary data pin) receive edge.
0d = Default edge as per the protocol configuration setting in bit 2 (BCLK_POL) 1d = Inverted following edge (half cycle delay) with respect to the default edge setting |
6 | SASI_RX_USE_INT_FSYNC | R/W | 0x0 | Secondary ASI uses internal FSYNC for input data latching in controller mode configuration as applicable.
0d = Use external FSYNC for ASI protocol data latching 1d = Use internal FSYNC for ASI protocol data latching |
5 | SASI_RX_USE_INT_BCLK | R/W | 0x0 | Secondary ASI uses internal BCLK for input data latching in controller mode configuration.
0d = Use external BCLK for ASI protocol data latching 1d = Use internal BCLK for ASI protocol data latching |
4-0 | SASI_RX_OFFSET[4:0] | R/W | 0x0 | Secondary ASI data input MSB slot 0 offset (on the primary and secondary data pin).
0d = ASI data MSB location has no offset and is as per standard protocol 1d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of one BCLK cycle with respect to standard protocol 2d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of two BCLK cycles with respect to standard protocol 3d to 30d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset assigned as per configuration 31d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of 31 BCLK cycles with respect to standard protocol |
SASI_RX_CFG1 is shown in Figure 7-202 and described in Table 7-205.
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This register is the SASI RX configuration register 1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SASI_RX_CH8_SEL | SASI_RX_CH7_SEL | SASI_RX_CH6_SEL | SASI_RX_CH5_SEL | SASI_RX_CH4_SEL | SASI_RX_CH3_SEL | SASI_RX_CH2_SEL | SASI_RX_CH1_SEL |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SASI_RX_CH8_SEL | R/W | 0x0 | Secondary ASI input channel 8 select.
0d = Secondary ASI channel 8 input is on DIN 1d = Secondary ASI channel 8 input is on DIN2 |
6 | SASI_RX_CH7_SEL | R/W | 0x0 | Secondary ASI input channel 7 select.
0d = Secondary ASI channel 7 input is on DIN 1d = Secondary ASI channel 7 input is on DIN2 |
5 | SASI_RX_CH6_SEL | R/W | 0x0 | Secondary ASI input channel 6 select.
0d = Secondary ASI channel 6 input is on DIN 1d = Secondary ASI channel 6 input is on DIN2 |
4 | SASI_RX_CH5_SEL | R/W | 0x0 | Secondary ASI input channel 5 select.
0d = Secondary ASI channel 5 input is on DIN 1d = Secondary ASI channel 5 input is on DIN2 |
3 | SASI_RX_CH4_SEL | R/W | 0x0 | Secondary ASI input channel 4 select.
0d = Secondary ASI channel 4 input is on DIN 1d = Secondary ASI channel 4 input is on DIN2 |
2 | SASI_RX_CH3_SEL | R/W | 0x0 | Secondary ASI input channel 3 select.
0d = Secondary ASI channel 3 input is on DIN 1d = Secondary ASI channel 3 input is on DIN2 |
1 | SASI_RX_CH2_SEL | R/W | 0x0 | Secondary ASI input channel 2 select.
0d = Secondary ASI channel 2 input is on DIN 1d = Secondary ASI channel 2 input is on DIN2 |
0 | SASI_RX_CH1_SEL | R/W | 0x0 | Secondary ASI input channel 1 select.
0d = Secondary ASI channel 1 input is on DIN 1d = Secondary ASI channel 1 input is on DIN2 |
SASI_RX_CH1_CFG is shown in Figure 7-203 and described in Table 7-206.
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This register is the SASI RX Channel 1 configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SASI_RX_CH1_CFG | SASI_RX_CH1_SLOT_NUM[4:0] | |||||
R-00b | R/W-0b | R/W-00000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
5 | SASI_RX_CH1_CFG | R/W | 0x0 | Secondary ASI input channel 1 configuration.
0d = Secondary ASI channel 1 input is disabled 1d = Secondary ASI channel 1 input corresponds to DAC Channel 1 data |
4-0 | SASI_RX_CH1_SLOT_NUM[4:0] | R/W | 0x0 | Secondary ASI input channel 1 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I2S, LJ is left slot 15 16d = TDM is slot 16 or I2S, LJ is right slot 0 17d = TDM is slot 17 or I2S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is right slot 15 |
SASI_RX_CH2_CFG is shown in Figure 7-204 and described in Table 7-207.
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This register is the SASI RX Channel 2 configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SASI_RX_CH2_CFG | SASI_RX_CH2_SLOT_NUM[4:0] | |||||
R-00b | R/W-0b | R/W-00001b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
5 | SASI_RX_CH2_CFG | R/W | 0x0 | Secondary ASI input channel 2 configuration.
0d = Secondary ASI channel 2 input is disabled 1d = Secondary ASI channel 2 input corresponds to DAC Channel 2 data |
4-0 | SASI_RX_CH2_SLOT_NUM[4:0] | R/W | 0x1 | Secondary ASI input channel 2 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I2S, LJ is left slot 15 16d = TDM is slot 16 or I2S, LJ is right slot 0 17d = TDM is slot 17 or I2S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is right slot 15 |
SASI_RX_CH3_CFG is shown in Figure 7-205 and described in Table 7-208.
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This register is the SASI RX Channel 3 configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SASI_RX_CH3_CFG | SASI_RX_CH3_SLOT_NUM[4:0] | |||||
R-00b | R/W-0b | R/W-00010b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
5 | SASI_RX_CH3_CFG | R/W | 0x0 | Secondary ASI input channel 3 configuration.
0d = Secondary ASI channel 3 input is disabled 1d = Secondary ASI channel 3 input corresponds to DAC Channel 3 data |
4-0 | SASI_RX_CH3_SLOT_NUM[4:0] | R/W | 0x2 | Secondary ASI input channel 3 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I2S, LJ is left slot 15 16d = TDM is slot 16 or I2S, LJ is right slot 0 17d = TDM is slot 17 or I2S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is right slot 15 |
SASI_RX_CH4_CFG is shown in Figure 7-206 and described in Table 7-209.
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This register is the SASI RX Channel 4 configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SASI_RX_CH4_CFG | SASI_RX_CH4_SLOT_NUM[4:0] | |||||
R-00b | R/W-0b | R/W-00011b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
5 | SASI_RX_CH4_CFG | R/W | 0x0 | Secondary ASI input channel 4 configuration.
0d = Secondary ASI channel 4 input is disabled 1d = Secondary ASI channel 4 input corresponds to DAC Channel 4 data |
4-0 | SASI_RX_CH4_SLOT_NUM[4:0] | R/W | 0x3 | Secondary ASI input channel 4 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I2S, LJ is left slot 15 16d = TDM is slot 16 or I2S, LJ is right slot 0 17d = TDM is slot 17 or I2S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is right slot 15 |
SASI_RX_CH5_CFG is shown in Figure 7-207 and described in Table 7-210.
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This register is the SASI RX Channel 5 configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SASI_RX_CH5_CFG[1:0] | SASI_RX_CH5_SLOT_NUM[4:0] | |||||
R-0b | R/W-00b | R/W-00100b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
6-5 | SASI_RX_CH5_CFG[1:0] | R/W | 0x0 | Secondary ASI input channel 5 configuration.
0d = Secondary ASI channel 5 input is disabled 1d = Secondary ASI channel 5 input corresponds to DAC Channel 5 data 2d = Secondary ASI channel 5 input corresponds to ADC Channel 1 output loopback 3d = Reserved |
4-0 | SASI_RX_CH5_SLOT_NUM[4:0] | R/W | 0x4 | Secondary ASI input channel 5 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I2S, LJ is left slot 15 16d = TDM is slot 16 or I2S, LJ is right slot 0 17d = TDM is slot 17 or I2S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is right slot 15 |
SASI_RX_CH6_CFG is shown in Figure 7-208 and described in Table 7-211.
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This register is the SASI RX Channel 6 configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SASI_RX_CH6_CFG[1:0] | SASI_RX_CH6_SLOT_NUM[4:0] | |||||
R-0b | R/W-00b | R/W-00101b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
6-5 | SASI_RX_CH6_CFG[1:0] | R/W | 0x0 | Secondary ASI input channel 6 configuration.
0d = Secondary ASI channel 6 input is disabled 1d = Secondary ASI channel 6 input corresponds to DAC Channel 6 data 2d = Secondary ASI channel 6 input corresponds to ADC Channel 2 output loopback 3d = Secondary ASI channel 6 input corresponds to ICLA device 1 data |
4-0 | SASI_RX_CH6_SLOT_NUM[4:0] | R/W | 0x5 | Secondary ASI input channel 6 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I2S, LJ is left slot 15 16d = TDM is slot 16 or I2S, LJ is right slot 0 17d = TDM is slot 17 or I2S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is right slot 15 |
SASI_RX_CH7_CFG is shown in Figure 7-209 and described in Table 7-212.
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This register is the SASI RX Channel 7 configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SASI_RX_CH7_CFG[1:0] | SASI_RX_CH7_SLOT_NUM[4:0] | |||||
R-0b | R/W-00b | R/W-00110b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
6-5 | SASI_RX_CH7_CFG[1:0] | R/W | 0x0 | Secondary ASI input channel 7 configuration.
0d = Secondary ASI channel 7 input is disabled 1d = Secondary ASI channel 7 input corresponds to DAC Channel 7 data 2d = Secondary ASI channel 7 input corresponds to ADC Channel 3 output loopback 3d = Secondary ASI channel 7 input corresponds to ICLA device 2 data |
4-0 | SASI_RX_CH7_SLOT_NUM[4:0] | R/W | 0x6 | Secondary ASI input channel 7 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I2S, LJ is left slot 15 16d = TDM is slot 16 or I2S, LJ is right slot 0 17d = TDM is slot 17 or I2S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is right slot 15 |
SASI_RX_CH8_CFG is shown in Figure 7-210 and described in Table 7-213.
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This register is the SASI RX Channel 8 configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SASI_RX_CH8_CFG[1:0] | SASI_RX_CH8_SLOT_NUM[4:0] | |||||
R-0b | R/W-00b | R/W-00111b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
6-5 | SASI_RX_CH8_CFG[1:0] | R/W | 0x0 | Secondary ASI input channel 8 configuration.
0d = Secondary ASI channel 8 input is disabled 1d = Secondary ASI channel 8 input corresponds to DAC Channel 8 data 2d = Secondary ASI channel 8 input corresponds to ADC Channel 4 output loopback 3d = Secondary ASI channel 8 input corresponds to ICLA device 3 data |
4-0 | SASI_RX_CH8_SLOT_NUM[4:0] | R/W | 0x7 | Secondary ASI input channel 8 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0 1d = TDM is slot 1 or I2S, LJ is left slot 1 2d to 14d = Slot assigned as per configuration 15d = TDM is slot 15 or I2S, LJ is left slot 15 16d = TDM is slot 16 or I2S, LJ is right slot 0 17d = TDM is slot 17 or I2S, LJ is right slot 1 18d to 30d = Slot assigned as per configuration 31d = TDM is slot 31 or I2S, LJ is right slot 15 |
CLK_CFG12 is shown in Figure 7-211 and described in Table 7-214.
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This register is the clock configuration register 12.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PDIV_CLKSRC_SEL[1:0] | PASI_BCLK_DIV_CLK_SEL[2:0] | RESERVED | |||||
R/W-00b | R/W-000b | R-000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | PDIV_CLKSRC_SEL[1:0] | R/W | 0x0 | Source clock selection for PLL PDIV Divider.
0d = PLL_PDIV_IN_CLK is Primary ASI BCLK 1d = PLL_PDIV_IN_CLK is Secondary ASI BCLK 2d = PLL_PDIV_IN_CLK is CCLK 3d = PLL_PDIV_IN_CLK is internal Oscillator Clock |
5-3 | PASI_BCLK_DIV_CLK_SEL[2:0] | R/W | 0x0 | Primary ASI BCLK divider clock source selection.
0d = Primary ASI BCLK divider clock source is PLL output 1d = Reserved 2d = Primary ASI BCLK divider clock source is secondary ASI BCLK 3d = Primary ASI BCLK divider clock source is CCLK 4d = Primary ASI BCLK divider clock source is internal oscillator clock 5d = Primary ASI BCLK divider clock source is DSP clock 6d to 7d = Reserved |
2-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
CLK_CFG13 is shown in Figure 7-212 and described in Table 7-215.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SASI_BCLK_DIV_CLK_SEL[2:0] | RESERVED | |||||
R-0b | R/W-000b | R-0000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
6-4 | SASI_BCLK_DIV_CLK_SEL[2:0] | R/W | 0x0 | Secondaary ASI BCLK divider clock source selection.
0d = Secondaary ASI BCLK divider clock source is PLL output 1d = Secondaary ASI BCLK divider clock source is primary ASI BCLK 2d = Reserved 3d = Secondaary ASI BCLK divider clock source is CCLK 4d = Secondaary ASI BCLK divider clock source is internal oscillator clock 5d = Secondaary ASI BCLK divider clock source is DSP clock 6d to 7d = Reserved |
3-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
CLK_CFG14 is shown in Figure 7-213 and described in Table 7-216.
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This register is the clock configuration register 14.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIG_NM_DIV_CLK_SRC_SEL[1:0] | ANA_NM_DIV_CLK_SRC_SEL[1:0] | RESERVED | RESERVED | ||||
R/W-00b | R/W-01b | R-00b | R-00b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | DIG_NM_DIV_CLK_SRC_SEL[1:0] | R/W | 0x0 | Source clock selection for DIG NMDIV CLK clock.
0d = DIG NM divider input clock is Primary ASI BCLK 1d = DIG NM divider input clock is Secondary ASI BCLK 2d = DIG NM divider input clock is CCLK 3d = DIG NM divider input clock is internal oscillator clock |
5-4 | ANA_NM_DIV_CLK_SRC_SEL[1:0] | R/W | 0x1 | Source clock selection for NMDIV CLK clock.
0d = NM divider input clock is PLL Output 1d = NM divider input clock is PLL Output 2d = NM divider input clock is DIG NM Divider Clock Source 3d = NM divider input clock is Primary ASI BCLK (Low Jitter Path) |
3-2 | RESERVED | R | 0x0 | Reserved bits; Write only reset values |
1-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset values |
CLK_CFG15 is shown in Figure 7-214 and described in Table 7-217.
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This register is the clock configuration register 15.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PLL_PDIV[7:0] | |||||||
R/W-00000001b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | PLL_PDIV[7:0] | R/W | 0x1 | PLL pre-scaler P-divider value (Don't care when auto detection is enabled)
0d = PLL PDIV value is 256 1d = PLL PDIV value is 1 2d = PLL PDIV value is 2 3d to 254d = PLL PDIV value is as per configuration 255d = PLL PDIV value is 255 |
CLK_CFG16 is shown in Figure 7-215 and described in Table 7-218.
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This register is the clock configuration register 16.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PLL_JMUL_MSB | PLL_DIV_CLK_DIG_BY_2 | PLL_DMUL_MSB[5:0] | |||||
R/W-0b | R/W-0b | R/W-000000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PLL_JMUL_MSB | R/W | 0x0 | PLL integer portion J-multiplier value MSB bit. (Don't care when auto detection is enabled) |
6 | PLL_DIV_CLK_DIG_BY_2 | R/W | 0x0 | PLL DIV clock divide by 2 configuration
0d = No divide/2 inside PLL 1d = PLL does a divide/2 |
5-0 | PLL_DMUL_MSB[5:0] | R/W | 0x0 | PLL fractional portion D-multiplier value MSB bits. (Don't care when auto detection is enabled) |
CLK_CFG17 is shown in Figure 7-216 and described in Table 7-219.
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This register is the clock configuration register 17.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PLL_DMUL_LSB[7:0] | |||||||
R/W-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | PLL_DMUL_LSB[7:0] | R/W | 0x0 | PLL fractional portion D-multiplier value LSB byte. Above D-multiplier value MSB bits (PLL_DMUL_MSB) along with this LSB byte (PLL_DMUL_LSB) is concatenated to determine final D-multiplier value. (Don't care when auto detection is enabled)
0d = PLL DMUL value is 0 1d = PLL DMUL value is 1 2d = PLL DMUL value is 2 3d to 9998d = PLL JMUL value is as per configuration 9999d = PLL JMUL value is 9999 10000d to 16383d = Reserved; Don't use |
CLK_CFG18 is shown in Figure 7-217 and described in Table 7-220.
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This register is the clock configuration register 18.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PLL_JMUL_LSB[7:0] | |||||||
R/W-00001000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | PLL_JMUL_LSB[7:0] | R/W | 0x8 | PLL integer portion J-multiplier value LSB byte. Above J-multiplier value MSB bit (PLL_JMUL_MSB) along with this LSB byte (PLL_JMUL_LSB) is concatenated to determine fianl J-multiplier value. (Don't care when auto detection is enabled)
0d = Reserved; Don't use 1d = PLL JMUL value is 1 2d = PLL JMUL value is 2 3d to 510d = PLL JMUL value is as per configuration 511d = PLL JMUL value is 511 |
CLK_CFG19 is shown in Figure 7-218 and described in Table 7-221.
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This register is the clock configuration register 19.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NDIV[2:0] | PDM_DIV[2:0] | RESERVED | |||||
R/W-001b | R/W-000b | R-00b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | NDIV[2:0] | R/W | 0x1 | NDIV divider value. (Don't care when auto detection is enabled)
0d = NDIV value is 8 1d = NDIV value is 1 2d = NDIV value is 2 3d to 6d = NDIV value is as per configuration 7d = NDIV value is 7 |
4-2 | PDM_DIV[2:0] | R/W | 0x0 | PDM divider value. (Don't care when auto detection is enabled)
0d = PDM_DIV value is 1 1d = PDM_DIV value is 2 2d = PDM_DIV value is 4 3d = PDM_DIV value is 8 4d = PDM_DIV value is 16 5d-7d Reserved |
1-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset values |
CLK_CFG20 is shown in Figure 7-219 and described in Table 7-222.
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This register is the clock configuration register 20.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDIV[5:0] | DIG_ADC_MODCLK_DIV[1:0] | ||||||
R/W-000001b | R/W-00b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | MDIV[5:0] | R/W | 0x1 | MDIV divider value. (Don't care when auto detection is enabled)
0d = MDIV value is 64 1d = MDIV value is 1 2d = MDIV value is 2 3d to 62d = MDIV value is as per configuration 63d = MDIV value is 63 |
1-0 | DIG_ADC_MODCLK_DIV[1:0] | R/W | 0x0 | ADC modulator clock divider value. (Don't care when auto detection is enabled)
0d = DIG_ADC_MODCLK_DIV value is 1 1d = DIG_ADC_MODCLK_DIV value is 2 2d = DIG_ADC_MODCLK_DIV value is 4 3d = Reserved |
CLK_CFG21 is shown in Figure 7-220 and described in Table 7-223.
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This register is the clock configuration register 21.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DIG_DAC_MODCLK_DIV[1:0] | RESERVED | PASI_BDIV_MSB | SASI_BDIV_MSB | RESERVED | ||
R-00b | R/W-00b | R-0b | R/W-0b | R/W-0b | R-0b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0x0 | Reserved bits; Write only reset values |
5-4 | DIG_DAC_MODCLK_DIV[1:0] | R/W | 0x0 | DAC modulator clock divider value. (Don't care when auto detection is enabled)
0d = DIG_DAC_MODCLK_DIV value is 1 1d = DIG_DAC_MODCLK_DIV value is 2 2d = DIG_DAC_MODCLK_DIV value is 4 3d = Reserved |
3 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
2 | PASI_BDIV_MSB | R/W | 0x0 | Primary ASI BCLK divider value MSB bit. (Don't care when auto detection is enabled) |
1 | SASI_BDIV_MSB | R/W | 0x0 | Secondary ASI BCLK divider value MSB bit. (Don't care when auto detection is enabled) |
0 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
CLK_CFG22 is shown in Figure 7-221 and described in Table 7-224.
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This register is the clock configuration register 18.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PASI_BDIV_LSB[7:0] | |||||||
R/W-00000001b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | PASI_BDIV_LSB[7:0] | R/W | 0x1 | Secondary ASI BCLK divider value. (Don't care when auto detection is enabled)
0d = SASI BCLK divider value is 512 1d = SASI BCLK divider value is 1 2d = SASI BCLK divider value is 2 3d to 62d = SASI BCLK divider value is as per configuration 63d = SASI BCLK divider value is 511 |
CLK_CFG23 is shown in Figure 7-222 and described in Table 7-225.
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This register is the clock configuration register 18.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SASI_BDIV_LSB[7:0] | |||||||
R/W-00000001b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | SASI_BDIV_LSB[7:0] | R/W | 0x1 | Secondary ASI BCLK divider value. (Don't care when auto detection is enabled)
0d = SASI BCLK divider value is 512 1d = SASI BCLK divider value is 1 2d = SASI BCLK divider value is 2 3d to 62d = SASI BCLK divider value is as per configuration 63d = SASI BCLK divider value is 511 |
CLK_CFG24 is shown in Figure 7-223 and described in Table 7-226.
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This register is the clock configuration register 21.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ANA_NM_DIV[5:0] | ||||||
R-00b | R/W-000001b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
5-0 | ANA_NM_DIV[5:0] | R/W | 0x1 | Analog N-M DIV divider value. (Don't care when auto detection is enabled)
0d = ANA_NM_DIV value is 64 1d = ANA_NM_DIV value is 1 2d = ANA_NM_DIV value is 2 3d to 62d = ANA_NM_DIV value is as per configuration 63d = NDIV value is 63 |
CLK_CFG30 is shown in Figure 7-224 and described in Table 7-227.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NDIV_EN | MDIV_EN | PDM_DIV_EN | ||||
R-00000b | R/W-0b | R/W-0b | R/W-0b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
2 | NDIV_EN | R/W | 0x0 | NDIV divider enable
0d = divider disabled 1d = divider enabled |
1 | MDIV_EN | R/W | 0x0 | MDIV divider enable
0d = divider disabled 1d = divider enabled |
0 | PDM_DIV_EN | R/W | 0x0 | PDM divider enable
0d = divider disabled 1d = divider enabled |
CLK_CFG31 is shown in Figure 7-225 and described in Table 7-228.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIG_ADC_DEM_DIV_EN | DIG_ADC_MODCLK_DIV_EN | DIG_DAC_DEM_DIV_EN | DIG_DAC_MODCLK_DIV_EN | PASI_BDIV_EN | SASI_BDIV_EN | PASI_FSYNC_DIV_EN | SASI_FSYNC_DIV_EN |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DIG_ADC_DEM_DIV_EN | R/W | 0x0 | ADC DEM divider enable
0d = divider disabled 1d = divider enabled |
6 | DIG_ADC_MODCLK_DIV_EN | R/W | 0x0 | ADC MODCLK divider enable
0d = divider disabled 1d = divider enabled |
5 | DIG_DAC_DEM_DIV_EN | R/W | 0x0 | DAC DEM divider enable
0d = divider disabled 1d = divider enabled |
4 | DIG_DAC_MODCLK_DIV_EN | R/W | 0x0 | DAC MODCLK divider enable
0d = divider disabled 1d = divider enabled |
3 | PASI_BDIV_EN | R/W | 0x0 | PASI BDIV divider enable
0d = divider disabled 1d = divider enabled |
2 | SASI_BDIV_EN | R/W | 0x0 | SASI BDIV divider enable
0d = divider disabled 1d = divider enabled |
1 | PASI_FSYNC_DIV_EN | R/W | 0x0 | PASI FSYNC DIV divider enable
0d = divider disabled 1d = divider enabled |
0 | SASI_FSYNC_DIV_EN | R/W | 0x0 | SASI FSYNC DIV divider enable
0d = divider disabled 1d = divider enabled |
CLKOUT_CFG1 is shown in Figure 7-226 and described in Table 7-229.
Return to the Summary Table.
This register is the CLKOUT configuration register 1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLKOUT_CLK_SEL[2:0] | ||||||
R-00000b | R/W-000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |
2-0 | CLKOUT_CLK_SEL[2:0] | R/W | 0x0 | General Purpose CLKOUT divider clock source selection.
0d = Source clock is PLL output 1d = Source clock is primary ASI BCLK 2d = Source clock is secondary ASI BCLK 3d = Source clock is CCLK 4d = Source clock is internal oscillator clock 5d = Source clock is DSP clock 6d to 7d = Reserved |
CLKOUT_CFG2 is shown in Figure 7-227 and described in Table 7-230.
Return to the Summary Table.
This register is the CLKOUT configuration register 2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLKOUT_DIV_EN | CLKOUT_DIV[6:0] | ||||||
R/W-0b | R/W-0000001b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CLKOUT_DIV_EN | R/W | 0x0 | CLKOUT divider enable.
0d = CLKOUT divider disabled 1d = CLKOUT divider enabled |
6-0 | CLKOUT_DIV[6:0] | R/W | 0x1 | CLKOUT DIV divider value.
0d = CLKOUT_DIV value is 128 1d = CLKOUT_DIV value is 1 2d = CLKOUT_DIV value is 2 3d to 126d = CLKOUT_DIV value is as per configuration 127d = CLKOUT_DIV value is 127 |
BSTCLK_CFG1 is shown in Figure 7-228 and described in Table 7-231.
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This register is the Boost clock configuration register 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BST_CLK_FREQ_SEL | BST_CLK_SRC_AUTO_DIS | BST_CLK_SRC_MANUAL_SEL | BST_CLK_EN_AUTO_DIS | BST_CLK_MANUAL_EN | BST_CLK_MANUAL_DIV[1:0] | |
R-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-00b | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved bit; Write only reset value |
6 | BST_CLK_FREQ_SEL | R/W | 0x0 | Boost clock frequency mode
0d = Boost clock frequency is ~6MHz 1d = Boost clock frequency is ~3MHz |
5 | BST_CLK_SRC_AUTO_DIS | R/W | 0x0 | Boost divider source clock auto selection disable
0d = Boost divider source clock auto-selection based on clock detection scheme 1d = Boost divider source clock auto-selection disabled and selected based on BST_CLK_SRC_SEL |
4 | BST_CLK_SRC_MANUAL_SEL | R/W | 0x0 | Boost clock source manual selection (don't care in auto mode)
0d = Boost clock generated based on Audio clock available for ADC/DAC 1d = Boost clock generated based on internal oscillator clock |
3 | BST_CLK_EN_AUTO_DIS | R/W | 0x0 | Boost divider source clock auto selection disable
0d = Boost divider auto-enabled 1d = Boost divider enabled/disabled based on manual control using BST_CLK_MANUAL_EN |
2 | BST_CLK_MANUAL_EN | R/W | 0x0 | Boost divider manual enable (don't care in auto mode)
0d = Boost divider disabled 1d = Boost divider enabled |
1-0 | BST_CLK_MANUAL_DIV[1:0] | R/W | 0x0 | Boost divider value (don't care in auto mode)
0d = Boost divider value is 1 1d = Boost divider value is 2 2d = Boost divider value is 4 3d = Boost divider value is 8 |
SARCLK_CFG1 is shown in Figure 7-229 and described in Table 7-232.
Return to the Summary Table.
This register is the SAR clock configuration register 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SAR_CLK_FREQ_SEL[1:0] | SAR_CLK_SRC_AUTO_DIS | SAR_CLK_SRC_MANUAL_SEL | SAR_CLK_EN_AUTO_DIS | SAR_CLK_MANUAL_EN | SAR_CLK_MANUAL_DIV[1:0] | ||
R/W-00b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-00b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | SAR_CLK_FREQ_SEL[1:0] | R/W | 0x0 | SAR clock frequency mode
0d = SAR clock frequency is ~6MHz 1d = SAR clock frequency is ~3MHz 2d = SAR clock frequency is ~1.5MHz 3d = SAR clock frequency is ~12MHz (valid only when SAR clock is generated directly using internal oscilator clock |
5 | SAR_CLK_SRC_AUTO_DIS | R/W | 0x0 | SAR divider source clock auto selection disable
0d = SAR divider source clock auto-selection based on clock detection scheme 1d = SAR divider source clock auto-selection disabled and selected based on BST_CLK_SRC_SEL |
4 | SAR_CLK_SRC_MANUAL_SEL | R/W | 0x0 | SAR clock source manual selection (don't care in auto mode)
0d = SAR clock generated based on Audio clock available for ADC/DAC 1d = SAR clock generated based on internal oscillator clock |
3 | SAR_CLK_EN_AUTO_DIS | R/W | 0x0 | SAR divider source clock auto selection disable
0d = SAR divider auto-enabled 1d = SAR divider enabled/disabled based on manual control using BST_CLK_EN |
2 | SAR_CLK_MANUAL_EN | R/W | 0x0 | SAR divider manual enable (don't care in auto mode)
0d = SAR divider disabled 1d = SAR divider enabled |
1-0 | SAR_CLK_MANUAL_DIV[1:0] | R/W | 0x0 | SAR divider value (don't care in auto mode)
0d = SAR divider value is 1 1d = SAR divider value is 2 2d = SAR divider value is 4 3d = SAR divider value is 8 |
ADC_OVRLD_FLAG is shown in Figure 7-230 and described in Table 7-233.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADC_CH1_OVRLD_LTCH | ADC_CH2_OVRLD_LTCH | ADC_CH1_OVRLD_LIVE | ADC_CH2_OVRLD_LIVE | RESERVED | |||
R-0b | R-0b | R-0b | R-0b | R-0000b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | ADC_CH1_OVRLD_LTCH | R | 0x0 | ADC CH1 OVRLD fault (self clearing bit).
0b = No ADC CH1 OVRLD fault 1b = ADC CH1 OVRLD fault |
6 | ADC_CH2_OVRLD_LTCH | R | 0x0 | ADC CH2 OVRLD fault (self clearing bit).
0b = No ADC CH2 OVRLD fault 1b = ADC CH2 OVRLD fault |
5 | ADC_CH1_OVRLD_LIVE | R | 0x0 | ADC CH1 OVRLD fault (self clearing bit).
0b = No ADC CH1 OVRLD fault 1b = ADC CH1 OVRLD fault |
4 | ADC_CH2_OVRLD_LIVE | R | 0x0 | ADC CH2 OVRLD fault (self clearing bit).
0b = No ADC CH2 OVRLD fault 1b = ADC CH2 OVRLD fault |
3-0 | RESERVED | R | 0x0 | Reserved bits; Write only reset value |