JAJSNP6 January 2024 TAC5312-Q1
ADVANCE INFORMATION
Each input of the TAC5312-Q1 features highly comprehensive DC fault diagnostics that can be configured to detect fault conditions in the DC-coupled input configuration and trigger an interrupt request to a host processor. Diagnostics are enabled for each channel by configuring DIAG_CFG0, P1_R70. For channels with diagnostics enabled, the input pins are scanned automatically by an integrated SAR ADC with a programmable repetition rate. The repetition rate can be configured using the REP_RATE, P1_R74_D[7:6] register bits. For fastest fault response time and also to get better signal integrity and signal chain performance for the record channel, REP_RATE must be configured to 0 (non-default setting). The diagnostic processor averages eight consecutive samples per test to improve noise performance. The DC fault diagnostics is not supported in the AC-coupled input configuration.
The device features various programmable threshold registers, P1_R71 to P1_R72, which can by configured by the host processor to define the fault region for a different category of fault condition detection. Additionally, there is also a debounce feature, configured with FAULT_DBNCE_SEL, P1_R74_D[3:2]. This feature sets the number of consecutive scan counts where the fault condition occurs before the latched status register is tripped, thus reducing false triggers by transient events. The device also has a moving average feature, P1_R75, which continuously averages out the newly measured data with old measured data and thus reduces the false triggers by any short-duration transient events.