Digital audio data flows between the host processor and the TAC5312-Q1 on the digital audio serial interface (ASI), or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation, support for I²S or left-justified protocols format, programmable data length options, very flexible controller-target configurability for bus clock lines, and the ability to communicate with multiple devices within a system directly.

The TAC5312-Q1 supports up to two ASI Interfaces. Secondary ASI Clock and Data Pins can be configured by setting GPIO's. Frame Sync of two ASI's must be synchronous.

The bus protocol TDM, I²S, or left-justified (LJ) format can be selected for primary ASI by using the PASI_FORMAT[1:0], P0_R26_D[7:6] register bits. As shown in Table 6-1 and.Table 6-2, these modes are all most significant byte (MSB)-first, pulse code modulation (PCM) data format, with the output channel data word-length programmable as 16, 20, 24, or 32 bits by configuring the PASI_WLEN[1:0], P0_R26_D[5:4] register bits.

The frame sync pin, FSYNC, is used in this audio bus protocol to define the beginning of a frame and has the same frequency as the output data sample rates. The bit clock pin, BCLK, is used to clock out the digital audio data across the serial bus. The number of bit-clock cycles in a frame must accommodate multiple device active output channels with the programmed data word length.

A frame consists of multiple time-division channel slots (up to 32) to allow all input/output channel audio data transmissions to be completed on the audio bus by a device or multiple devices sharing the same audio bus. The device supports up to eight input channels and eight output channels that can be configured on the primary ASI bus to place their audio data on bus slot 0 to slot 31. Table 6-3 lists the output channel-1 slot configuration settings. In I²S and LJ mode, the slots are divided into two sets, left-channel slots, and right-channel slots, as described in the Section 6.3.1.2.2 and Section 6.3.1.2.3 sections.

Similarly, the slot assignment setting for output channel 2 to channel 8 can be done using the PASI_TX_CH2_SLOT (P0_R31) to PASI_TX_CH8_SLOT (P0_R37) registers and for input channel 1 to channel 8 by using the PASI_RX_CH1_SLOT(P0_R40) to PAS_RX_CH8_SLOT(P0_R47), respectively.

The slot word length is the same as the primary ASI channel word length set for the device. The output channel data word length must be set to the same value for all TAC5312-Q1 devices if all devices share the same ASI bus in a system. The maximum number of slots possible for the ASI bus in a system is limited by the available bus bandwidth, which depends upon the BCLK frequency, output data sample rate used, and the channel data word length configured.

The device also includes a feature that offsets the start of the slot data transfer concerning the frame sync by up to 31 cycles of the bit clock. Offset can be configured independently for input and output data paths. Table 6-4 and Table 6-5lists the programmable offset configuration settings for transmission and receive paths respectively.

The device also features the ability to invert the polarity of the frame sync pin, FSYNC, used to transfer the audio data as compared to the default FSYNC polarity used in standard protocol timing. This feature can be set using the PASI_FSYNC_POL, P0_R26_D3 register bit. Similarly, the device can invert the polarity of the bit clock pin, BCLK, which can be set using the PASI_BCLK_POL, P0_R26_D2 register bit.

In addition, the word clock and bit clock can be independently configured in either Controller or Target mode, for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC sampling frequencies.