9 Power Supply Recommendations

The power-supply sequence between the IOVDD, BSTVDD and AVDD rails can be applied in any order. However, after all supplies are stable, then only initiate the I²C or SPI transactions to initialize the device.

For the supply power-up requirement, t₁, t₂ and t₃ must be at least 2 ms to allow the device to initialize the internal registers. For the supply power-down requirement, t₄, t₅ and t₆ must be at least 10 ms. This timing (as shown in Figure 9-1) allows the device to ramp down the volume on the record data, power down the analog and digital blocks, and put the device into shutdown mode. The device can also be immediately put into shutdown mode by ramping down power supplies, but doing so causes an abrupt shutdown.

Figure 9-1 Power-Supply Sequencing Requirement Timing Diagram

Make sure that the supply ramp rate is slower than 0.1V/µs and that the wait time between a power-down and a power-up event is at least 100 ms. For supply ramp rate slower than 0.1 V/ms, host device must apply a software reset as first transaction before doing any device configuration. Make sure all digital input pins are at valid input levels and not toggling during supply sequencing.

The TAC5312-Q1 supports a single AVDD supply operation by integrating an on-chip digital regulator, DREG, and an analog regulator, AREG.