JAJSNP5 January 2024 TAC5411-Q1
ADVANCE INFORMATION
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ADC PERFORMANCE FOR LINE INPUT RECORDING | |||||||
Differential input full-scale DC signal voltage | AC-coupled input, input fault diagnostic not supported | 10 | VRMS | ||||
DC-coupled input, DC common-mode voltage INxP = INxM = 7.1 V, input fault diagnostic supported | |||||||
Single-ended input full-scale DC signal voltage | AC-coupled input, input fault diagnostic not supported | 5 | VRMS | ||||
DC-coupled input, DC common-mode voltage INxP = INxM = 7.1 V, input fault diagnostic supported | |||||||
SNR | Signal-to-noise ratio, A-weighted(1)(2) | IN1 differential AC-coupled input selected and AC signal shorted to ground, 0-dB channel gain | 108 | dB | |||
IN1 differential DC-coupled input selected and AC signal shorted to ground, 0-dB channel gain | 108 | ||||||
DR | Dynamic range, A-weighted(2) | IN1 differential AC-coupled input selected and –60-dB full-scale AC signal input, 0-dB channel gain | 108 | dB | |||
IN1 differential DC-coupled input selected and –60-dB full-scale AC signal input, 0-dB channel gain | 108 | ||||||
THD+N | Total harmonic distortion(2) | IN1 differential AC-coupled input selected and –1-dB full-scale AC signal input, 0-dB channel gain | –95 | TBD | dB | ||
IN1 differential DC-coupled input selected and –1-dB full-scale AC signal input, 0-dB channel gain | –95 | ||||||
ADC PERFORMANCE FOR MICROPHONE INPUT RECORDING | |||||||
ADC OTHER PARAMETERS | |||||||
Input impedance | Differential input, between INxP and INxM | 66.6 | kΩ | ||||
Single-ended input, between INxP and INxM | 33.3 | ||||||
Offset | Shorted Input. | TBD | mV | ||||
Digital volume control range | Programmable 0.5-dB steps | –120 | 42 | dB | |||
Input Signal Bandwidth | Upto 192KSPS FS Rate | 0.46 | FS | ||||
>192KSPS | 90 | kHz | |||||
Output data sample rate | Programmable | 3.675 | 768 | kHz | |||
Output data sample word length | Programmable | 16 | 32 | Bits | |||
Digital high-pass filter cutoff frequency | First-order IIR filter with programmable coefficients, –3-dB point (default setting) |
2 | Hz | ||||
PSRR | Power-supply rejection ratio | 100-mVPP, 1-kHz sinusoidal signal on AVDD, differential input selected, 0-dB channel gain | 92 | dB | |||
CMRR | Common-mode rejection ratio | Differential microphone input selected, 0-dB channel gain, 1-VRMS AC input, 1-kHz signal on both pins and measure level at output, CHx_CFG0 D3-2 register bits set to 2b'10 to configure device in high CMRR performance mode | 80 | dB | |||
MICROPHONE BIAS | |||||||
MICBIAS noise | BW = 20 Hz to 20 kHz, A-weighted, 1-µF capacitor between MICBIAS and AVSS | 20 | µVRMS | ||||
MICBIAS voltage | Programmable 0.5-V steps | 3 | 10 | V | |||
MICBIAS current drive | MICBIAS voltage 10 V | 30 | mA | ||||
MICBIAS load regulation | MICBIAS voltage 10 V, measured up to maximum load | 0 | 1 | % | |||
MICBIAS over current protection threshold | MICBIAS voltage 10 V | 35 | mA | ||||
INPUT DIAGNOSTICS | |||||||
Fault monitoring repetition rate | Programmable, DC-coupled input | 1 | 4 | 8 | ms | ||
Fault response time | Fault monitoring repetition rate 4-ms, DC-coupled input | 16 | ms | ||||
Threshold voltage for (INxx – AVSS) input shorted to ground | Programmable 60-mV steps, DC-coupled input | 0 | 900 | mV | |||
Threshold voltage for (INxP – INxM) input shorted together | Programmable 30-mV steps, DC-coupled input | 0 | 450 | mV | |||
Threshold voltage for (MICBIAS – INxx) input shorted to MICBIAS | Programmable 30-mV steps, DC-coupled input | 0 | 450 | mV | |||
Threshold voltage for (VBAT – INxx) input shorted to VBAT_IN | Programmable 30-mV steps, DC-coupled input | 0 | 450 | mV | |||
DAC Performance for Line Output/Head Phone Playback | |||||||
Full Scale Output Voltage | Differential output between OUTxP and OUTxM, AVDD=3.3V | 2 | VRMS | ||||
Single-ended Output, AVDD=3.3V | 1 | ||||||
Pseudo Differential Output between OUTxP and OUTxM, AVDD=3.3V | 1 | ||||||
SNR | Signal-to-noise ratio, A-weighted(1)(2) | Differential Output, 0dBFS Signal, AVDD=3.3V | 119 | dB | |||
Single Ended Output, 0dBFS Signal, AVDD=3.3V | 110 | ||||||
Pseudo Differential Output, 0dBFS Signal, AVDD=3.3V | 110 | ||||||
Differential Output, 0dBFS Signal, AVDD=3.3V, 0dBFS Signal, Power Tune Mode | 114 | ||||||
Single Ended Output, 0dBFS Signal, AVDD=3.3V, Power Tune Mode | 105 | ||||||
Pseudo Differential Output, 0dBFS Signal, AVDD=3.3V, Power Tune Mode | 104 | ||||||
DR | Dynamic range, A-weighted(2) | Differential Output, -60dBFS Signal, AVDD=3.3V | 119 | dB | |||
Single Ended Output, -60dBFS Signal, AVDD=3.3V | 110 | ||||||
Pseudo Differential Output, -60dBFS Signal, AVDD=3.3V | 110 | ||||||
Differential Output, -60dBFS Signal, AVDD=3.3V, 0dBFS Signal, Power Tune Mode | 114 | ||||||
Single Ended Output, -60dBFS Signal, AVDD=3.3V, Power Tune Mode | 105 | ||||||
Pseudo Differential Output, -60dBFS Signal, AVDD=3.3V, Power Tune Mode | 104 | ||||||
THD+N | Total harmonic distortion(2) | –95 | dB | ||||
Head Phone Load Range | 16 | Ω | |||||
Line Out Load Range | 600 | Ω | |||||
Channel gain control range | Programmable 1-dB steps | –6 | 12 | dB | |||
DAC Channel OTHER PARAMETERS | |||||||
Output Offset | 0 Input | 0.5 | mV | ||||
Output Common Mode | Common Mode Level for OUTxP and OUTxM AVDD=3.3V (Register Configurable) | Common Mode Level for OUTxP and OUTxM AVDD=3.3V | 1.625 | V | |||
Common Mode Error | DC Error in Common Mode Voltage | ±20 | mV | ||||
Digital volume control range | Programmable 0.5-dB steps | –120 | 42 | dB | |||
Output Signal Bandwidth | Upto 192KSPS FS Rate | 0.46 | FS | ||||
>192KSPS | 90 | kHz | |||||
Input data sample rate | Programmable | 7.35 | 768 | kHz | |||
Input data sample word length | Programmable | 16 | 32 | Bits | |||
Digital high-pass filter cutoff frequency | First-order IIR filter with programmable coefficients, –3-dB point (default setting) |
2 | Hz | ||||
PSRR | Power-supply rejection ratio | 100-mVPP, 1-kHz sinusoidal signal on AVDD, differential input selected, 0-dB channel gain | 92 | dB | |||
Mute Attenuation | –130 | dB | |||||
Pout | Output Power Delivery | Single ended/Pseudo Differential RL=16 Ohms, THD+N<1% | 62.5 | mW | |||
DIGITAL I/O | |||||||
VIL | Low-level digital input logic voltage threshold | All digital pins except GPI1A, GPI2A, ADDRA, SDA and SCL, IOVDD 1.8-V operation | –0.3 | 0.35 x IOVDD | V | ||
All digital pins except GPI1A, GPI2A, ADDRA, SDA and SCL, IOVDD 3.3-V operation | –0.3 | 0.8 | |||||
VIH | High-level digital input logic voltage threshold | All digital pins except GPI1A, GPI2A, ADDRA, SDA and SCL, IOVDD 1.8-V operation | 0.65 x IOVDD | IOVDD + 0.3 | V | ||
All digital pins except GPI1A, GPI2A, ADDRA, SDA and SCL, IOVDD 3.3-V operation | 2 | IOVDD + 0.3 | |||||
VOL | Low-level digital output voltage | All digital pins except GPO1A, SDA and SCL, IOL = –2 mA, IOVDD 1.8-V operation | 0.45 | V | |||
All digital pins except GPO1A, SDA and SCL, IOL = –2 mA, IOVDD 3.3-V operation | 0.4 | ||||||
VOH | High-level digital output voltage | All digital pins except GPO1A, SDA and SCL, IOH = 2 mA, IOVDD 1.8-V operation | IOVDD – 0.45 | V | |||
All digital pins except GPO1A, SDA and SCL, IOH = 2 mA, IOVDD 3.3-V operation | 2.4 | ||||||
VIL(AVDD) | Low-level digital input logic voltage threshold | For Pins GPI1A, GPI2A, ADDRA | –0.3 | 0.35 x AVDD | V | ||
VIH(AVDD) | High-level digital input logic voltage threshold | For Pins GPI1A, GPI2A, ADDRA | 0.65 x AVDD | AVDD + 0.3 | V | ||
VOL(AVDD) | Low-level digital output voltage | For GPO1A Pin | 0.45 | V | |||
VOH(AVDD) | High-level digital output voltage | For GPO1A Pin | AVDD – 0.45 | V | |||
VIL(I2C) | Low-level digital input logic voltage threshold | SDA and SCL | –0.5 | 0.3 x IOVDD | V | ||
VIH(I2C) | High-level digital input logic voltage threshold | SDA and SCL | 0.7 x IOVDD | IOVDD + 0.5 | V | ||
VOL1(I2C) | Low-level digital output voltage | SDA, IOL(I2C) = –3 mA, IOVDD > 2 V | 0.4 | V | |||
VOL2(I2C) | Low-level digital output voltage | SDA, IOL(I2C) = –2 mA, IOVDD [char_not_recognized] 2 V | 0.2 x IOVDD | V | |||
IOL(I2C) | Low-level digital output current | SDA, VOL(I2C) = 0.4 V, standard-mode or fast-mode | 3 | mA | |||
SDA, VOL(I2C) = 0.4 V, fast-mode plus | 20 | ||||||
IIL | Input logic-low leakage for digital inputs | All digital pins, input = 0 V | –5 | 0.1 | 5 | µA | |
IIH | Input logic-high leakage for digital inputs | All digital pins, input = IOVDD | –5 | 0.1 | 5 | µA | |
CIN | Input capacitance for digital inputs | All digital pins | 5 | pF | |||
RPD | Pulldown resistance for digital I/O pins when asserted on | 20 | kΩ | ||||
TYPICAL SUPPLY CURRENT CONSUMPTION | |||||||
IAVDD | Current consumption in hardware shutdown mode | SHDNZ = 0, all device external clocks stopped | 0.5 | µA | |||
IBSTVDD, or IHVDD | 0.1 | ||||||
IIOVDD | 0.1 | ||||||
IAVDD | Current consumption in sleep mode (software shutdown mode) | All device external clocks stopped | TBD | µA | |||
IBSTVDD, or IHVDD | 0.1 | ||||||
IIOVDD | 0.1 | ||||||
IAVDD | Current consumption when MICBIAS ON, MICBIAS voltage 10 V, 30 mA load, ADC off | fS = 48 kHz, BCLK = 256 [char_not_recognized] fS | TBD | mA | |||
IBSTVDD | TBD | ||||||
IHVDD | TBD | ||||||
IIOVDD | 0.01 | ||||||
IAVDD | Current consumption with ADC 2-channel operation at fS 16-kHz, MICBIAS off, PLL on, BCLK = 512 [char_not_recognized] fS | TBD | mA | ||||
IBSTVDD, or IHVDD | 0 | ||||||
IIOVDD | 0.1 | ||||||
IAVDD | Current consumption with ADC 2-channel operation at fS 48-kHz, MICBIAS on, PLL off, BCLK = 512 [char_not_recognized] fS | TBD | mA | ||||
IBSTVDD, or IHVDD | 0 | ||||||
IIOVDD | 0.1 | ||||||
IAVDD | Current consumption with DAC to HP 2-channel operation at fS 16-kHz, MICBIAS off, PLL on, BCLK = 512 [char_not_recognized] fS | TBD | mA | ||||
IBSTVDD, or IHVDD | 0 | ||||||
IIOVDD | 0.2 | ||||||
IAVDD | Current consumption with DAC to HP 2-channel operation at fS 48-kHz, MICBIAS off, PLL off, BCLK = 512 [char_not_recognized] fS | TBD | mA | ||||
IBSTVDD, or IHVDD | 0 | ||||||
IIOVDD | TBD |