JAJSSN9 December   2023 TAD5212

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
        4. 7.3.1.4 Phase-Locked Loop (PLL) and Clock Generation
        5. 7.3.1.5 Output Channel Configurations
        6. 7.3.1.6 Reference Voltage
        7. 7.3.1.7 Programmable Microphone Bias
        8. 7.3.1.8 Signal-Chain Processing
          1. 7.3.1.8.1 DAC Signal-Chain
            1. 7.3.1.8.1.1 Programmable Channel Gain and Digital Volume Control
            2. 7.3.1.8.1.2 Programmable Channel Gain Calibration
            3. 7.3.1.8.1.3 Programmable Digital High-Pass Filter
            4. 7.3.1.8.1.4 Programmable Digital Biquad Filters
            5. 7.3.1.8.1.5 Programmable Digital Mixer
            6. 7.3.1.8.1.6 Configurable Digital Interpolation Filters
              1. 7.3.1.8.1.6.1 Linear Phase Filters
                1. 7.3.1.8.1.6.1.1 Sampling Rate: 16 kHz or 14.7 kHz
                2. 7.3.1.8.1.6.1.2 Sampling Rate: 24 kHz or 22.05 kHz
                3. 7.3.1.8.1.6.1.3 Sampling Rate: 32 kHz or 29.4 kHz
                4. 7.3.1.8.1.6.1.4 Sampling Rate: 48 kHz or 44.1 kHz
                5. 7.3.1.8.1.6.1.5 Sampling Rate: 96 kHz or 88.2 kHz
                6. 7.3.1.8.1.6.1.6 Sampling Rate: 384 kHz or 352.8 kHz
        9. 7.3.1.9 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1 TAD5212_P0 Registers
      2. 7.5.2 TAD5212_P1 Registers
      3. 7.5.3 TAD5212_P3 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM target mode and PLL on (unless otherwise noted)
PARAMETERTEST CONDITIONSMINNOMMAXUNIT
DAC Performance for Line Output/Head Phone Playback
Full Scale Output VoltageDifferential output between OUTxP and OUTxM, AVDD=3.3V2VRMS
Differential Output between OUTxP and OUTxM, AVDD=1.8V1
Single-ended Output, AVDD=3.3V1
Single-ended Output, AVDD=1.8V0.5
Pseudo Differential Output between OUTxP and OUTxM, AVDD=3.3V1
Pseudo Differential Output between OUTxP and OUTxM, AVDD=1.8V0.5
SNRSignal-to-noise ratio, A-weighted(1)(2)Differential Output, 0dBFS Signal, AVDD=3.3V119dB
Single Ended Output, 0dBFS Signal, AVDD=3.3V111
Pseudo Differential Output, 0dBFS Signal, AVDD=3.3V110
Differential Output, 0dBFS Signal, AVDD=1.8V114
Single Ended Output, 0dBFS Signal, AVDD=1.8V105
Pseudo Differential Output, 0dBFS Signal, AVDD=1.8V104
Differential Output, 0dBFS Signal, AVDD=3.3V, 0dBFS Signal, Power Tune Mode112
Single Ended Output, 0dBFS Signal, AVDD=3.3V, Power Tune Mode102
Pseudo Differential Output, 0dBFS Signal, AVDD=3.3V, Power Tune Mode101
Differential Output, 0dBFS Signal, AVDD=1.8V, Power Tune Mode108
Single Ended Output, 0dBFS Signal, AVDD=1.8V, Power Tune Mode97
Pseudo Differential Output, 0dBFS Signal, AVDD=1.8V, Power Tune Mode96
DRDynamic range, A-weighted(2)Differential Output, -60dBFS Signal, AVDD=3.3V119dB
Single Ended Output, -60dBFS Signal, AVDD=3.3V111
Pseudo Differential Output, -60dBFS Signal, AVDD=3.3V110
Differential Output, -60dBFS Signal, AVDD=1.8V114
Single Ended Output, -60dBFS Signal, AVDD=1.8V105
Pseudo Differential Output, -60dBFS Signal, AVDD=1.8V104
Differential Output, -60dBFS Signal, AVDD=3.3V, 0dBFS Signal, Power Tune Mode112
Single Ended Output, -60dBFS Signal, AVDD=3.3V, Power Tune Mode102
Pseudo Differential Output, -60dBFS Signal, AVDD=3.3V, Power Tune Mode101
Differential Output, -60dBFS Signal, AVDD=1.8V, Power Tune Mode108
Single Ended Output, -60dBFS Signal, AVDD=1.8V, Power Tune Mode97
Pseudo Differential Output, -60dBFS Signal, AVDD=1.8V, Power Tune Mode96
THD+NTotal harmonic distortion(2) -95dB
Head Phone Load Range16Ω
Line Out Load Range600Ω
Channel gain control rangeProgrammable 1-dB steps–612dB
Analog Bypass to Line Out/Head Phone Amplifier
Input impedanceDifferential input, between INxP and INxM8.8kΩ
Single-ended input, between INxP and INxM4.4
Differential input, between INxP and INxM, 40k Mode40k
Single-ended input, between INxP and INxM, 40k Mode20k
Single Ended Full Scale OutputAVDD=3.3VAVDD=3.3V1Vrms
Differential Full Scale OutputAVDD=3.3V2Vrms
AVDD=1.8V1Vrms
Gain Error0.1dB
Noise, A-WeightedIdle Channel, AC Coupled Input Shorted to Ground, Fully Differential output4.5µVRMS
Noise, A-WeightedIdle Channel, AC Coupled Input Shorted to Ground, Single Ended output6.3µVRMS
SNRSignal-to-noise ratio, A-weighted(1)(2)Idle Channel, AC Coupled Input Shorted to Ground, Fully Differential output, AVDD=3.3V113dB
SNRSignal-to-noise ratio, A-weighted(1)(2)Idle Channel, AC Coupled Input Shorted to Ground, Single Ended output, AVDD=3.3V104dB
THD+NTotal harmonic distortion(2)IN1 differential AC-coupled input selected and -1-dB full-scale AC signal input, 0-dB channel gaindB
DAC Channel OTHER PARAMETERS
Output Offset0 Input, Fully Differential Output0.2mV
Output Offset0 Input, Pseudo Differential Output0.4mV
Output Common ModeCommon Mode Level for OUTxP and OUTxM AVDD=1.8V (Register Configurable)0.9V
Output Common ModeCommon Mode Level for OUTxP and OUTxM AVDD=3.3V (Register Configurable)1.66V
Common Mode ErrorDC Error in Common Mode Voltage±10mV
Digital volume control rangeProgrammable 0.5-dB steps–12042dB
Output Signal BandwidthUpto 192KSPS FS Rate0.46FS
>192KSPS100kHz
Input data sample rateProgrammable3.675768kHz
Input data sample word lengthProgrammable1632Bits
Digital high-pass filter cutoff frequencyFirst-order IIR filter with programmable coefficients,
–3-dB point (default setting)		2Hz
Interchannel isolation–134dB
Interchannel gain mismatch0.1dB
Interchannel phase mismatch1-kHz sinusoidal signal0.01Degrees
PSRRPower-supply rejection ratio100-mVPP, 1-kHz sinusoidal signal on AVDD, differential input selected, 0-dB channel gain100dB
Mute Attenuation–130dB
PoutOutput Power DeliverySingle ended/Pseudo Differential RL=16 Ohms, THD+N<1%62.5mW
MICROPHONE BIAS
MICBIAS noiseBW = 20 Hz to 20 kHz, A-weighted, 1-µF capacitor between MICBIAS and AVSS2µVRMS
MICBIAS voltageBypass to AVDDAVDDV
MICBIAS voltageAVDD=1.8V1.375V
MICBIAS voltageAVDD=3.3V2.75V
DIGITAL I/O
VIL(SHDNZ)Low-level digital input logic voltage thresholdSHDNZ pin–0.30.25 × IOVDDV
VIH(SHDNZ)High-level digital input logic voltage thresholdSHDNZ pin0.75 × IOVDDIOVDD + 0.3V
VILLow-level digital input logic voltage thresholdAll digital pins except SDA and SCL, IOVDD 1.8-V operation–0.30.35 × IOVDDV
All digital pins except SDA and SCL, IOVDD 3.3-V operation–0.30.8
VIHHigh-level digital input logic voltage thresholdAll digital pins except SDA and SCL, IOVDD 1.8-V operation0.65 × IOVDDIOVDD + 0.3V
All digital pins except SDA and SCL, IOVDD 3.3-V operation2IOVDD + 0.3
VOLLow-level digital output voltageAll digital pins except SDA and SCL, IOL = –2 mA, IOVDD 1.8-V operation0.45V
All digital pins except SDA and SCL, IOL = –2 mA, IOVDD 3.3-V operation0.4
VOHHigh-level digital output voltageAll digital pins except SDA and SCL, IOH = 2 mA, IOVDD 1.8-V operationIOVDD – 0.45V
All digital pins except SDA and SCL, IOH = 2 mA, IOVDD 3.3-V operation2.4
VIL(I2C)Low-level digital input logic voltage thresholdSDA and SCL–0.50.3 × IOVDDV
VIH(I2C)High-level digital input logic voltage thresholdSDA and SCL0.7 × IOVDDIOVDD + 0.5V
VOL1(I2C)Low-level digital output voltageSDA, IOL(I2C) = –3 mA, IOVDD > 2 V0.4V
VOL2(I2C)Low-level digital output voltageSDA, IOL(I2C) = –2 mA, IOVDD ≤ 2 V0.2 x IOVDDV
IOL(I2C)Low-level digital output currentSDA, VOL(I2C) = 0.4 V, standard-mode or fast-mode3mA
SDA, VOL(I2C) = 0.4 V, fast-mode plus20
IILInput logic-low leakage for digital inputsAll digital pins, input = 0 V–50.15µA
IIHInput logic-high leakage for digital inputsAll digital pins, input = IOVDD–50.15µA
CINInput capacitance for digital inputsAll digital pins5pF
RPDPulldown resistance for digital I/O pins when asserted on20kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDDCurrent consumption in sleep mode (software shutdown mode)All device external clocks stoppedTBDµA
IIOVDD1
IAVDDCurrent consumption with DAC to HP 2-channel operation at fS 16-kHz, MICBIAS off, PLL on, BCLK = 512 × fSTBDmA
IIOVDD0.2
IAVDDCurrent consumption with DAC to HP 2-channel operation at fS 48-kHz, MICBIAS off, PLL off, BCLK = 512 × fSTBDmA
IIOVDDTBD
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter can result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, can affect dynamic specification values.