JAJSSN9 December   2023 TAD5212

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
        4. 7.3.1.4 Phase-Locked Loop (PLL) and Clock Generation
        5. 7.3.1.5 Output Channel Configurations
        6. 7.3.1.6 Reference Voltage
        7. 7.3.1.7 Programmable Microphone Bias
        8. 7.3.1.8 Signal-Chain Processing
          1. 7.3.1.8.1 DAC Signal-Chain
            1. 7.3.1.8.1.1 Programmable Channel Gain and Digital Volume Control
            2. 7.3.1.8.1.2 Programmable Channel Gain Calibration
            3. 7.3.1.8.1.3 Programmable Digital High-Pass Filter
            4. 7.3.1.8.1.4 Programmable Digital Biquad Filters
            5. 7.3.1.8.1.5 Programmable Digital Mixer
            6. 7.3.1.8.1.6 Configurable Digital Interpolation Filters
              1. 7.3.1.8.1.6.1 Linear Phase Filters
                1. 7.3.1.8.1.6.1.1 Sampling Rate: 16 kHz or 14.7 kHz
                2. 7.3.1.8.1.6.1.2 Sampling Rate: 24 kHz or 22.05 kHz
                3. 7.3.1.8.1.6.1.3 Sampling Rate: 32 kHz or 29.4 kHz
                4. 7.3.1.8.1.6.1.4 Sampling Rate: 48 kHz or 44.1 kHz
                5. 7.3.1.8.1.6.1.5 Sampling Rate: 96 kHz or 88.2 kHz
                6. 7.3.1.8.1.6.1.6 Sampling Rate: 384 kHz or 352.8 kHz
        9. 7.3.1.9 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1 TAD5212_P0 Registers
      2. 7.5.2 TAD5212_P1 Registers
      3. 7.5.3 TAD5212_P3 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.3 Detailed Design Procedure

This section describes the necessary steps to configure the TAD5212 for this specific application. The following steps provide a sequence of items that must be executed in the time between powering the device up and reading data from the device or transitioning from one mode to another mode of operation.

  1. Apply power to the device:
    1. Power up the IOVDD and AVDD power supplies
    2. Wait for at least 1ms to allow the device to initialize the internal registers.
    3. The device now goes into sleep mode (low-power mode < 10 µA)
  2. Transition from sleep mode to active mode whenever required for the operation:
    1. Wake up the device by writing to P0_R2 to disable sleep mode
    2. Wait for at least 1 ms to allow the device to complete the internal wake-up sequence
    3. Override the default configuration registers or programmable coefficients value as required (this step is optional)
    4. Enable all desired audio serial interface input/output channels by writing to P0_R40 to P0_R47 for DAC
    5. Power-up the DAC by writing to P0_R120
    6. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio

      This specific step can be done at any point in the sequence after step a.

      See the Section 7.3.1.4 section for supported sample rates and the BCLK to FSYNC ratio.

    7. The device recording data is now sent to the host processor using the TDM audio serial data bus and playback data from TDM is now played on the lineout
  3. Transition from active mode to sleep mode (again) as required in the system for low-power operation:
    1. Enter sleep mode by writing to P0_R2 to enable sleep mode
    2. Wait at least 6 ms (when FSYNC = 48 kHz) for the volume to ramp down and for all blocks to power down
    3. Read P0_R122 to check the device shutdown and sleep mode status
    4. If the device P0_R122_D[7:5] status bit is 3'b100 then stop FSYNC and BCLK in the system
    5. The device now goes into sleep mode (low-power mode < 10 µA) and retains all register values
  4. Transition from sleep mode to active mode (again) as required for the recording operation:
    1. Wake up the device by writing to P0_R2 to disable sleep mode
    2. Wait at least 1 ms to allow the device to complete the internal wake-up sequence
    3. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio
    4. The device recording data is now sent to the host processor using the TDM audio serial data bus and playback data from TDM is now played on the lineout
  5. Repeat step 4 and step 5 as required for mode transitions