SLASET8 December 2019 TAS2110
PRODUCTION DATA.
The TAS2110 supports alignment of limiter (including brown out prevention) dynamics across devices that share the same TDM bus. This ensures consistent gain between channels during limiting or brown out events since these dynamics are dependent on audio content, which can vary across channels. Each device can be configured to align to a specified number of other devices, which allows creation of groupings of devices that align only to each other. All devices in the same group must use the same setting.
Limiter activity is communicated via the limiter gain reduction parameter that can be optionally transmitted by each device on SDOUT in an 8-bit time slot. Gain reduction should be transmitted in adjacent time slots for all devices that are to be aligned beginning with the first slot that is specified by the ICLA_SLOT register. The order of the devices is not important as long as they are adjacent. The time slot for limiter gain reduction is configured by the GAIN_SLOT register and enabled by the GAIN_TX register bit.
The ICLA_SEN register specify which time slots should be listened to for gain alignment. This allows any number of devices between two and eight to be grouped together. At least two of these bits should be enabled for alignment to take place. The ICLA_USE_MAX register bit determines whether alignment is based on the maximum or minimum gain reduction value from the group of enabled devices. If the BIL_ICLA_EN is enabled the # of slots will be double what is selected. For example if time-slot 0,1, and 2 are used for gain alignment. Then time-slots 3, 4, and 5 will be used for brownout-current alignment.
To enable the inter chip limiter alignment feature, the ICLA_GAIN_EN register bit should be asserted high and all devices should be configured with identical limiter and brown out prevention settings. Limiter gain reduction transmission should be enabled on all devices as described above.
ICLA_GAIN_EN | VALUE |
---|---|
0
|
Disabled (default) |
1
|
Enabled |
ICLA_MODE | VALUE |
---|---|
00
|
Use the maximum gain reduction of the ICLA group (default) |
01
|
Use the minimum gain reduction of the ICLA group |
10-11
|
Reserved |
ICLA_GAIN_SLOT[5:0] | STARTING TIME SLOT |
---|---|
0x00
|
Time Slot 0 |
0x01
|
Time Slot 1 |
0x02
|
Time Slot 2 |
...
|
... |
0x3F
|
Time Slot 63 |
REGISTER BIT | DESCRIPTION | BIT VALUE | STATE |
---|---|---|---|
ICLA_GAIN_SEN[0] | Time Slot = ICLA_GAIN_SLOT. When enabled, the limiter will include this time slot in the alignment group. |
0
|
Disabled (default) |
1
|
Enabled | ||
ICLA_GAIN_SEN[[1] | Time Slot = ICLA_GAIN_SLOT + 1. When enabled, the limiter will include this time slot in the alignment group. |
0
|
Disabled (default) |
1
|
Enabled | ||
ICLA_GAIN_SEN[[2] | Time Slot = ICLA_GAIN_SLOT + 2. When enabled, the limiter will include this time slot in the alignment group. |
0
|
Disabled (default) |
1
|
Enabled | ||
ICLA_GAIN_SEN[3] | Time Slot = ICLA_GAIN_SLOT + 3. When enabled, the limiter will include this time slot in the alignment group. |
0
|
Disabled (default) |
1
|
Enabled |