SLASFC6 August   2024 TAS2120

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
          3. 6.3.1.4.3 VDD Y-bridge
          4. 6.3.1.4.4 Class-H Boost
        5. 6.3.1.5 2S Battery Mode
        6. 6.3.1.6 External PVDD Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4 Boost
      5. 6.4.5 Supply Voltage Monitors
      6. 6.4.6 Thermal Protection
      7. 6.4.7 Clocks and PLL
        1. 6.4.7.1 Auto clock based wakeup and clock errors
      8. 6.4.8 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Mono/Stereo Configuration
        2. 7.2.2.2 Boost Converter Passive Devices
        3. 7.2.2.3 EMI Passive Devices
        4. 7.2.2.4 Miscellaneous Passive Devices
      3. 7.2.3 Application Performance Plots
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2 Typical Application

Diagrams below shows the typical application connections for 1S and 2S Li-Ion battery and for the external PVDD or 3S Battery connection. VBAT_SNS pin connection is optional and if not used, this pin should be grounded. SEL1 is used for HW Mode selection or I2C Mode selection of the Device.

System can use same 1.8V supply source to power the IOVDD and VDD if required. The decoupling caps C2 and C3 should still be placed close to the device pins.

VBAT, VDD, PVDD power rails are critical for device performance and wide trace should be used from the source PMIC to these pins to minimize parasitic inductance. Supply ripple should be kept at minimum for these rails and should be connected to common supply planes.

TAS2120 Application Diagram for 1S Battery system Figure 7-1 Application Diagram for 1S Battery system

TAS2120 Application Diagram for 2S Battery system Figure 7-2 Application Diagram for 2S Battery system
TAS2120 Application Diagram for External PVDD or 3S Battery system Figure 7-3 Application Diagram for External PVDD or 3S Battery system
Table 7-1 Recommended External Components
Component Description Specification Min Typ Max Unit
L1 Boost Convertor Inductor Inductance, 20% Tolerance 0.47 1 µH
Saturation current 5.3 A
L2, L3 Optional EMI Filter Inductors (must use C10, C11 if L2, L3 are used) DC Current 2 A
C1, C2 DREG, IOVDD decap Capacitance, 20% tolerance 1 µF
Voltage rating 2 6.3 V
C3 VDD decap Capacitance, 20% tolerance 2.2 µF
Voltage rating 2 6.3 V
C4 VBAT decap Capacitance, 20% tolerance 1 µF
Voltage rating 6.3 10 V
C5 1S Battery Power decap Capacitance, 20% tolerance 10 µF
Voltage rating 6.3 10 V
C5a 2S Battery Power decap Capacitance, 20% tolerance 10 µF
Voltage rating 10 16 V
C6 PVDD Low ESL decap Capacitance, 20% tolerance 0.1 µF
Voltage rating 16 25 V
C7, C8, C12 PVDD Power decap Capacitance, 20% tolerance 10 µF
Voltage rating 16 25 V
Effective total PVDD Capacitance at 13V DC after deratings for 1S battery systems 3 µF
Effective total PVDD Capacitance at 13V DC after deratings for 2S battery system

Note: C12 is not required for 2S system to meet the derating spec.

 2 µF
C9 GREG decap Capacitance, 20% tolerance 0.1 µF
Voltage rating 6.3 10 V
C10, C11 Optional EMI Filter capacitors (must use L2, L3 if C10, C11 are used) Voltage rating 2xPVDD V