JAJSDJ0C
February 2013 – September 2021
TAS2505
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
I2S/LJF/RJF Timing in Master Mode
6.7
I2S/LJF/RJF Timing in Slave Mode
6.8
DSP Timing in Master Mode
6.9
DSP Timing in Slave Mode
6.10
I2C Interface Timing
6.11
SPI Interface Timing
6.12
Typical Characteristics
6.12.1
Class D Speaker Driver Performance
6.12.2
HP Driver Performance
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Audio Analog I/O
7.3.2
Audio DAC and Audio Analog Outputs
7.3.3
DAC
7.3.4
POR
7.3.5
CLOCK Generation and PLL
7.4
Device Functional Modes
7.4.1
Digital Pins
7.4.2
Analog Pins
7.4.3
Multifunction Pins
7.4.4
Analog Signals
7.4.4.1
Analog Inputs AINL and AINR
7.4.5
DAC Processing Blocks — Overview
7.4.6
Digital Mixing and Routing
7.4.7
Analog Audio Routing
7.4.8
5V LDO
7.4.9
Digital Audio and Control Interface
7.4.9.1
Digital Audio Interface
7.4.9.2
Control Interface
7.4.9.2.1
I2C Control Mode
7.4.9.2.2
SPI Digital Interface
7.4.9.3
Device Special Functions
7.5
Register Map
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Typical Configuration
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Curves
8.2.2
Circuit Configuration With Internal LDO
8.2.2.1
Design Requirements
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
Community Resources
11.4
Trademarks
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RGE|24
MPQF124G
サーマルパッド・メカニカル・データ
RGE|24
QFND136Y
発注情報
jajsdj0c_oa
jajsdj0c_pm
7
Detailed Description