TAS2552 4.0-W Class-D Mono Audio Amplifier with Class-G Boost and Speaker Sense

1 Features

Analog or Digital Input Mono Boosted Class-D Amplifier
4.0 W into 8 Ω Load from 4.2 V Supply (1% THD+N)
Efficiency of 85% at Rated Power
I2S, Left-Justified, Right-Justified, DSP, PDM, and TDM Input and Output Interface
Input Sample Rates from 8 kHz to 192 kHz
High Efficiency Class-G Boost Converter
- Automatically Adjusts Class-D Supply
Built-In Speaker Sense
- Measures Speaker Current and Voltage
- Measures VBAT and VBOOST Voltages
Built-In Automatic Gain Control (AGC)
- Limits Battery Current Consumption
Adjustable Class-D Switching Edge-Rate Control
Power Supplies
- Boost Input: 3.0 V to 5.5 V
- Analog: 1.65 V to 1.95 V
- Digital I/O: 1.5 V to 3.6 V
Thermal and Short-Circuit Protection
I²C Interface for Register Control
Stereo Configuration Using Two TAS2552s
- I²C Address Select Terminal (ADDR)
2.855 mm x 2.575 mm, 0.4 mm Pitch 30-Ball WCSP

2 Applications

Mobile Phones
PND
Portable Audio Docks
Tablets
Gaming Devices

3 Description

The TAS2552 is a high efficiency Class-D audio power amplifier with advanced battery current management and an integrated Class-G boost converter. The device constantly measures the current and voltage across the load and provides a digital stream of this information.

The Class-G boost converter generates the Class-D amplifier supply rail. During low Class-D output power, the boost improves efficiency by deactivating and connecting VBAT directly to the Class-D amplifier supply. When high power audio is required, the boost quickly activates to provide significantly louder audio than a stand-alone amplifier connected directly to the battery.

The AGC automatically adjusts Class-D gain to reduce battery current at end-of-charge voltages, preventing output clipping, distortion and early system shutdown. The fixed gain is adjustable via I²C. The gain range is -7 dB to +24 dB in 1 dB steps.

In addition to a differential mono analog input, the TAS2552 has built-in a 16-bit D/A converter used with a digital input. Moving the D/A converter from the digital host processor into the integrated amplifier process provides better dynamic performance at lower system cost. Additionally, since the PCB routing is digital rather than analog, sensitivity to external perturbations such as GSM frame-rate noise is decreased at the system level.

Device Information

ORDER NUMBER	PACKAGE	BODY SIZE
TAS2552YFF	WCSP (30)	2.855 mm x 2.575 mm

4 Revision History

Changes from A Revision (February 2014) to B Revision

Added clarification on EN Pin Function and ConfigurationGo
Changed VBAT MAX = 2.45 V. Added footnote to avoid VBAT reset.Go
Added clarification on wait time regarding DEV_RESET RegisterGo
Added clarification on VBAT reset range for normal operation mode.Go

Changes from * Revision (January 2014) to A Revision

Changed from Product Preview to Production Data Go

5 Pin Configuration and Functions

30-Ball WCSP

YFF Package

(Top View)

Pin Functions

TERMINAL		INPUT/OUTPUT/POWER	DESCRIPTION
NAME	BALL WCSP	INPUT/OUTPUT/POWER	DESCRIPTION
PGND	A1	P	Power ground. Connect to high current ground plane.
OUT–	A2	O	Inverting Class D output.
OUT+	A3	O	Non-inverting Class D output.
PVDD	A4	P	Class-D power supply. Connected internally to VBOOST – do not drive this terminal externally.
VBOOST	A5	P	8.5 V boost output. Connected internally to PVDD – do not drive this terminal externally.
BIAS	B1	O	Mid-rail reference for Class D channel.
VSENSE–	B2	I	Inverting voltage sense input.
VSENSE+	B3	I	Non-inverting voltage sense input.
SW	B4,B5	I/O	Boost switch terminal.
AGND	C1,C2	P	Analog ground. Connect to low noise ground plane.
VREG	C3	O	High-side FET gate drive boost converter.
PGND	C4,C5	P	Power ground. Connect to high current ground plane.
VBAT	D1	P	Battery power supply. Connect to 3.0 V to 5.5 V battery supply.
AIN–	D2	I	Inverting analog input.
DIN	D3	I	Audio serial data input. Format is I2S, LJF, RJF, or TDM data.
ADDR	D4	I	I²C address select terminal. Set ADDR = GND for device 7-bit address 0x40; set ADDR = IOVDD for 7-bit address 0x41.
SDA	D5	I/O	I²C control bus data.
AVDD	E1	P	Analog low voltage supply terminal. Connect to 1.65 V to 1.95 V supply.
AIN+	E2	I	Non-inverting analog input.
DOUT	E3	O	Serial I/V digital output. Format is I2S, LJF, RJF, TDM, or undecimated PDM data.
IVCLKIN	E4	I	Serial clock input for undecimated PDM I/V data.
SCL	E5	I	I²C control bus clock.
EN⁽¹⁾	F2	I	Device enable (HIGH = Normal Operation, LOW = Standby)
WCLK	F3	I	Audio serial word clock.
BCLK	F4	I	Audio serial bit clock.
MCLK	F5	I	External master clock.
IOVDD	F1	P	Supply for digital input and output levels. Voltage range is 1.5 V to 3.6 V.

(1) Wait a minimum of 1ms after EN is pulled high or DEV_RESET is issued before accessing the control interface. EN=low will erase the TAS2552 device configuration. The TAS2552 device must be configured (see Initialization) after EN=high.