JAJSD19B
August 2015 – February 2019
TAS2555
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
概略回路図
4
改訂履歴
5
概要(続き)
6
Device Comparison Table
7
Pin Configuration and Functions
Pin Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
I2C Timing Requirements
8.7
SPI Timing Requirements
8.8
I2S/LJF/RJF Timing in Master Mode
8.9
I2S/LJF/RJF Timing in Slave Mode
8.10
DSP Timing in Master Mode
8.11
DSP Timing in Slave Mode
8.12
Typical Characteristics
9
Parameter Measurement Information
10
Detailed Description
10.1
Overview
10.2
Functional Block Diagram
10.3
Feature Description
10.3.1
General I2C Operation
10.3.2
Single-Byte and Multiple-Byte Transfers
10.3.3
Single-Byte Write
10.3.4
Multiple-Byte Write and Incremental Multiple-Byte Write
10.3.5
Single-Byte Read
10.3.6
Multiple-Byte Read
10.3.7
General SPI Operation
10.3.8
Class-D Edge Rate Control
10.3.9
Battery Tracking AGC
10.3.10
Configurable Boost Current Limit (ILIM)
10.3.10.1
Fault Protection
10.3.10.1.1
OverCurrent
10.3.10.1.2
Analog Undervoltage
10.3.10.1.3
Overtemperature
10.3.10.1.4
Clocking Faults
10.3.10.2
Brownout
10.3.10.3
Spread Spectrum vs Synchronized
10.3.10.4
IRQs and Flags
10.3.10.5
Software Reset
10.3.10.6
PurePath Console 3 Software TAS2555 Application
10.4
Device Functional Modes
10.4.1
Audio Digital I/O Interface
10.4.1.1
Right-Justified Mode (RJF)
10.4.1.2
Left-Justified Mode (LJF)
10.4.1.3
I2S Mode
10.4.1.4
DSP Mode
10.4.2
TDM Mode
10.4.3
Device Digital Processing Modes
10.4.3.1
ROM Mode 1
10.4.3.2
ROM Mode 2
10.4.3.3
SmartAmp Mode
10.4.4
Low Power Sleep Mode
10.5
Programming
10.5.1
Code Loading and CRC check
10.5.2
Device Power Up, Power Down, Mute and Un-mute Sequence
11
Application and Implementation
11.1
Application Information
11.2
Typical Applications
11.2.1
Design Requirements
11.2.1.1
Detailed Design Procedure
11.2.1.1.1
Mono/Stereo Configuration
11.2.1.1.2
Boost Converter Passive Devices
11.2.1.1.3
EMI Passive Devices
11.2.1.1.4
Miscellaneous Passive Devices
11.2.2
Application Performance Plots
11.3
Initialization Set Up
12
Power Supply Recommendations
12.1
Power Supplies
12.2
Power Supply Sequencing
13
Layout
13.1
Layout Guidelines
13.2
Layout Example
14
Register Map
14.1
Register Map Summary
14.2
Book 0 Page 0
14.2.1
Book 0 / Page 0 / Register 0: Page Select Register - 0x00 / 0x00 / 0x00 (B0_P0_R0)
14.2.2
Book 0 / Page 0 / Register 1: Software Reset Register - 0x00 / 0x00 / 0x01 (B0_P0_R1)
14.2.3
Book 0 / Page 0 / Register 2-3: Reserved Registers - 0x00 / 0x00 / 0x02-0x03 (B0_P0_R2-3)
14.2.4
Book 0 / Page 0 / Register 4: Power Control Register - 0x00 / 0x00 / 0x04 (B0_P0_R4)
14.2.5
Book 0 / Page 0 / Register 5: Power Control Register 2 - 0x00 / 0x00 / 0x05 (B0_P0_R5)
14.2.6
Book 0 / Page 0 / Register 6: Speaker Control Register - 0x00 / 0x00 / 0x06 (B0_P0_R6)
14.2.7
Book 0 / Page 0 / Register 7: Mute Register - 0x00 / 0x00 / 0x07 (B0_P0_R7)
14.2.8
Book 0 / Page 0 / Register 8: Channel Control Register - 0x00 / 0x00 / 0x08 (B0_P0_R8)
14.2.9
Book 0 / Page 0 / Register 9-31: Reserved Registers - 0x00 / 0x00 / 0x09-0x1F (B0_P0_R9-31)
14.2.10
Book 0 / Page 0 / Register 32: CRC Checksum Register - 0x00 / 0x00 / 0x20 (B0_P0_R32)
14.2.11
Book 0 / Page 0 / Register 33: Checksum Reset Register - 0x00 / 0x00 / 0x21 (B0_P0_R33)
14.2.12
Book 0 / Page 0 / Register 34: Device DSP Mode Register - 0x00 / 0x00 / 0x22 (B0_P0_R34)
14.2.13
Book 0 / Page 0 / Register 35-39: Reserved Registers - 0x00 / 0x00 / 0x23-0x27 (B0_P0_R35-R39)
14.2.14
Book 0 / Page 0 / Register 40: Class-D SSM Mode Register - 0x00 / 0x00 / 0x28 (B0_P0_R40)
14.2.15
Book 0 / Page 0 / Register 41: Reserved Registers - 0x00 / 0x00 / 0x29 (B0_P0_R41)
14.2.16
Book 0 / Page 0 / Register 42: Digital Playback Control Register - 0x00 / 0x00 / 0x2A (B0_P0_R42)
14.2.17
Book 0 / Page 0 / Register 43: Current Limit Register - 0x00 / 0x00 / 0x2B (B0_P0_R43)
14.2.18
Book 0 / Page 0 / Register 44: Clock Error Control 1 Register - 0x00 / 0x00 / 0x2C (B0_P0_R44)
14.2.19
Book 0 / Page 0 / Register 45: Clock Error Control 2 Register - 0x00 / 0x00 / 0x2D (B0_P0_R45)
14.2.20
Book 0 / Page 0 / Register 46: Clock Error Control 3 Register - 0x00 / 0x00 / 0x2E (B0_P0_R46)
14.2.21
Book 0 / Page 0 / Register 47-99: Reserved Registers - 0x00 / 0x00 / 0x2F-0x63 (B0_P0_R47-R99)
14.2.22
Book 0 / Page 0 / Register 100: Power Up Flag Register - 0x00 / 0x00 / 0x64 (B0_P0_R100)
14.2.23
Book 0 / Page 0 / Register 101-103: Reserved Registers - 0x00 / 0x00 / 0x65-0x67 (B0_P0_R101-R103)
14.2.24
Book 0 / Page 0 / Register 104: Interrupt Flags DAC & OCP/OTP Sticky Register - 0x00 / 0x00 / 0x68 (B0_P0_R104)
14.2.25
Book 0 / Page 0 / Register 105-107: Reserved Registers - 0x00 / 0x00 / 0x69-0x6B (B0_P0_R105-R107)
14.2.26
Book 0 / Page 0 / Register 108: DSP Interrupt Output Sticky Register - 0x00 / 0x00 / 0x6C (B0_P0_R108)
14.2.27
Book 0 / Page 0 / Register 109-120: Reserved Registers - 0x00 / 0x00 / 0x6D-0x78 (B0_P0_R109-R120)
14.2.28
Book 0 / Page 0 / Register 121: Power Modes Register - 0x00 / 0x00 / 0x79 (B0_P0_R121)
14.2.29
Book 0 / Page 0 / Register 122-126: Reserved Registers - 0x00 / 0x00 / 0x7A-0x7E (B0_P0_R122-R126)
14.2.30
Book 0 / Page 0 / Register 127: Book Selection Register - 0x00 / 0x00 / 0x7F (B0_P0_R127)
14.3
Book 0 Page 1
14.3.1
Book 0 / Page 1 / Register 0: Page Select Register - 0x00 / 0x01 / 0x00 (B0_P1_R0)
14.3.2
Book 0 / Page 1 / Register 1: ASI1 DAC Format Register - 0x00 / 0x01 / 0x01 (B0_P1_R1)
14.3.3
Book 0 / Page 1 / Register 2: ASI1 ADC Format Register - 0x00 / 0x01 / 0x02 (B0_P1_R2)
14.3.4
Book 0 / Page 1 / Register 3: ASI1 Offset Register - 0x00 / 0x00 / 0x03 (B0_P1_R3)
14.3.5
Book 0 / Page 1 / Register 4-6: Reserved Registers - 0x00 / 0x01 / 0x04-0x06 (B0_P1_R4-6)
14.3.6
Book 0 / Page 1 / Register 7: ASI1 ADC Path Register - 0x00 / 0x01 / 0x07 (B0_P1_R7)
14.3.7
Book 0 / Page 1 / Register 8: ASI1 DAC BCLK Register - 0x00 / 0x01 / 0x08 (B0_P1_R8)
14.3.8
Book 0 / Page 1 / Register 9: ASI1 DAC WCLK Register - 0x00 / 0x01 / 0x09 (B0_P1_R9)
14.3.9
Book 0 / Page 1 / Register 10: ASI1 ADC BCLK Register - 0x00 / 0x01 / 0x0A (B0_P1_R10)
14.3.10
Book 0 / Page 1 / Register 11: ASI1 ADC WCLK Register - 0x00 / 0x01 / 0x0B (B0_P1_R11)
14.3.11
Book 0 / Page 1 / Register 12: ASI1 DIN/DOUT MUX Register - 0x00 / 0x01 / 0x0C (B0_P1_R12)
14.3.12
Book 0 / Page 1 / Register 13: ASI1 BDIV Clock Select Register - 0x00 / 0x01 / 0x0D (B0_P1_R13)
14.3.13
Book 0 / Page 1 / Register 14: ASI1 BDIV Clock Ratio Register - 0x00 / 0x01 / 0x0E (B0_P1_R14)
14.3.14
Book 0 / Page 1 / Register 15: ASI1 WDIV Clock Ratio Register - 0x00 / 0x01 / 0x0F (B0_P1_R15)
14.3.15
Book 0 / Page 1 / Register 16: ASI1 DAC Clock Output Register - 0x00 / 0x01 / 0x10 (B0_P1_R16)
14.3.16
Book 0 / Page 1 / Register 17: ASI1 ADC Clock Output Register - 0x00 / 0x01 / 0x11 (B0_P1_R17)
14.3.17
Book 0 / Page 1 / Register 18-20: Reserved Registers - 0x00 / 0x01 / 0x12-0x14 (B0_P1_R18-20)
14.3.18
Book 0 / Page 1 / Register 21: ASI2 DAC Format Register - 0x00 / 0x01 / 0x15 (B0_P1_R21)
14.3.19
Book 0 / Page 1 / Register 22: ASI2 ADC Format Register - 0x00 / 0x01 / 0x16 (B0_P1_R22)
14.3.20
Book 0 / Page 1 / Register 23: ASI2 Offset Register - 0x00 / 0x01 / 0x17 (B0_P1_R23)
14.3.21
Book 0 / Page 1 / Register 24-26: Reserved Registers - 0x00 / 0x01 / 0x18-0x1A (B0_P1_R24-26)
14.3.22
Book 0 / Page 1 / Register 27: ASI2 ADC Path Register - 0x00 / 0x01 / 0x1B (B0_P1_R27)
14.3.23
Book 0 / Page 1 / Register 28: ASI2 DAC BCLK Register - 0x00 / 0x01 / 0x1C (B0_P1_R28)
14.3.24
Book 0 / Page 1 / Register 29: ASI2 DAC WCLK Register - 0x00 / 0x01 / 0x1D (B0_P1_R29)
14.3.25
Book 0 / Page 1 / Register 30: ASI2 ADC BCLK Register - 0x00 / 0x01 / 0x1E (B0_P1_R30)
14.3.26
Book 0 / Page 1 / Register 31: ASI2 ADC WCLK Register - 0x00 / 0x01 / 0x1F (B0_P1_R31)
14.3.27
Book 0 / Page 1 / Register 32: ASI2 DIN/DOUT MUX - 0x00 / 0x01 / 0x20 (B0_P1_R32)
14.3.28
Book 0 / Page 1 / Register 33: ASI2 BDIV Clock Select Register - 0x00 / 0x01 / 0x21 (B0_P1_R33)
14.3.29
Book 0 / Page 1 / Register 34: ASI2 BDIV Clock Ratio Register - 0x00 / 0x01 / 0x22 (B0_P1_R34)
14.3.30
Book 0 / Page 1 / Register 35: ASI2 WDIV Clock Ratio Register - 0x00 / 0x01 / 0x23 (B0_P1_R35)
14.3.31
Book 0 / Page 1 / Register 36: ASI2 DAC Clock Output Register - 0x00 / 0x01 / 0x24 (B0_P1_R36)
14.3.32
Book 0 / Page 1 / Register 37: ASI2 ADC Clock Output Register - 0x00 / 0x01 / 0x25 (B0_P1_R37)
14.3.33
Book 0 / Page 1 / Register 38-60: Reserved Registers - 0x00 / 0x01 / 0x26-0x3C (B0_P1_R38-60)
14.3.34
Book 0 / Page 1 / Register 61: BCLK1_GPIO1 Pin Register - 0x00 / 0x01 / 0x3D (B0_P1_R61)
14.3.35
Book 0 / Page 1 / Register 62: WCLK1_GPIO2 Pin Register - 0x00 / 0x01 / 0x3E (B0_P1_R62)
14.3.36
Book 0 / Page 1 / Register 63: DOUT1_GPIO3 Pin Register - 0x00 / 0x01 / 0x3F (B0_P1_R63)
14.3.37
Book 0 / Page 1 / Register 64: IRQ_GPIO4 Pin Register - 0x00 / 0x01 / 0x40 (B0_P1_R64)
14.3.38
Book 0 / Page 1 / Register 65: BCLK2_GPIO5 Pin Register - 0x00 / 0x01 / 0x41 (B0_P1_R65)
14.3.39
Book 0 / Page 1 / Register 66: WCLK2_GPIO6 Pin Register - 0x00 / 0x01 / 0x42 (B0_P1_R66)
14.3.40
Book 0 / Page 1 / Register 67: DOUT2_GPIO7 Pin Register - 0x00 / 0x01 / 0x43 (B0_P1_R67)
14.3.41
Book 0 / Page 1 / Register 68: DIN2_GPIO8 Pin Register - 0x00 / 0x01 / 0x44 (B0_P1_R68)
14.3.42
Book 0 / Page 1 / Register 69: ICC_GPIO9 Pin(ICC_CLK) Register - 0x00 / 0x01 / 0x45 (B0_P1_R69)
14.3.43
Book 0 / Page 1 / Register 70: ICC_GPIO10 Pin Register - 0x00 / 0x01 / 0x46 (B0_P1_R70)
14.3.44
Book 0 / Page 1 / Register 71-76: Reserved Registers - 0x00 / 0x01 / 0x47-0x4C (B0_P1_R71-76)
14.3.45
Book 0 / Page 1 / Register 77: GPI Pins Register - 0x00 / 0x01 / 0x4D (B0_P1_R77)
14.3.46
Book 0 / Page 1 / Register 78: Reserved Register - 0x00 / 0x01 / 0x4E (B0_P1_R78)
14.3.47
Book 0 / Page 1 / Register 79: GPIO HIZ CTRL1 Register - 0x00 / 0x01 / 0x4F (B0_P1_R79)
14.3.48
Book 0 / Page 1 / Register 80: GPIO HIZ CTRL2 Register - 0x00 / 0x01 / 0x50 (B0_P1_R80)
14.3.49
Book 0 / Page 1 / Register 81: GPIO HIZ CTRL3 Register - 0x00 / 0x01 / 0x51 (B0_P1_R81)
14.3.50
Book 0 / Page 1 / Register 82: GPIO HIZ CTRL4 Register - 0x00 / 0x01 / 0x52 (B0_P1_R82)
14.3.51
Book 0 / Page 1 / Register 83: GPIO HIZ CTRL3 Register - 0x00 / 0x01 / 0x53 (B0_P1_R83)
14.3.52
Book 0 / Page 1 / Register 84-86: Reserved Registers - 0x00 / 0x01 / 0x54-0x56 (B0_P1_R84-86)
14.3.53
Book 0 / Page 1 / Register 87: GPIO Pin 1 Register - 0x00 / 0x01 / 0x57 (B0_P1_R87)
14.3.54
Book 0 / Page 1 / Register 88: GPIO Pin 2 Register - 0x00 / 0x01 / 0x58 (B0_P1_R88)
14.3.55
Book 0 / Page 1 / Register 89: GPIO Pin 3 Register - 0x00 / 0x01 / 0x59 (B0_P1_R89)
14.3.56
Book 0 / Page 1 / Register 90-107: Reserved Registers - 0x00 / 0x01 / 0x5A-0x6B (B0_P1_R84-86)
14.3.57
Book 0 / Page 1 / Register 108: Interrupt Control 1 Register - 0x00 / 0x01 / 0x6C (B0_P1_R108)
14.3.58
Book 0 / Page 1 / Register 109: Interrupt Control 2 Register - 0x00 / 0x01 / 0x6D (B0_P1_R109)
14.3.59
Book 0 / Page 1 / Register 110: Interrupt Control 3 Register - 0x00 / 0x01 / 0x6E (B0_P1_R110)
14.3.60
Book 0 / Page 1 / Register 111: Interrupt Control 4 Register - 0x00 / 0x01 / 0x6F (B0_P1_R111)
14.3.61
Book 0 / Page 1 / Register 112: Interrupt Control 5 Register - 0x00 / 0x01 / 0x70 (B0_P1_R112)
14.3.62
Book 0 / Page 1 / Register 113: Interrupt Control 6 Register - 0x00 / 0x01 / 0x71 (B0_P1_R113)
14.3.63
Book 0 / Page 1 / Register 114-127: Reserved Register - 0x00 / 0x01 / 0x72-0x7F (B0_P1_R127)
14.4
Book 0 Page 2
14.4.1
Book 0 / Page 2 / Register 0: Page Select Register - 0x00 / 0x02 / 0x00 (B0_P0_R0)
14.4.2
Book 0 / Page 2 / Register 1-5: Reserved Register - 0x00 / 0x02 / 0x01-0x05 (B0_P1_R1-5)
14.4.3
Book 0 / Page 2 / Register 6: Ramp Generator Frequency Register - 0x00 / 0x02 / 0x06 (B0_P2_R6)
14.4.4
Book 0 / Page 2 / Register 7-23: Reserved Register - 0x00 / 0x02 / 0x07-0x17 (B0_P1_R7-23)
14.4.5
Book 0 / Page 2 / Register 24: Inrush Optimization 1 Register - 0x00 / 0x02 / 0x18 (B0_P2_R24)
14.4.6
Book 0 / Page 2 / Register 25: Inrush Optimization 2 Register - 0x00 / 0x02 / 0x19 (B0_P2_R25)
14.4.7
Book 0 / Page 2 / Register 26: Inrush Optimization 3 Register - 0x00 / 0x02 / 0x1A (B0_P2_R25)
14.4.8
Book 0 / Page 2 / Register 27: Inrush Optimization 4 Register - 0x00 / 0x02 / 0x1B (B0_P2_R25)
14.4.9
Book 0 / Page 2 / Register 28-127: Reserved Register - 0x00 / 0x02 / 0x1C-0x7F (B0_P1_R28-127)
14.5
Book 100 Page 0
14.5.1
Book 100 / Page 0 / Register 0: Page Select Register - 0x64 / 0x00 / 0x00 (B100_P0_R0)
14.5.2
Book 100 / Page 0 / Register 1: DAC Interpolation Register - 0x64 / 0x00 / 0x01 (B100_P0_R1)
14.5.3
Book 100 / Page 0 / Register 2: ADC interpolation Register - 0x64 / 0x00 / 0x01 (B100_P0_R1)
14.5.4
Book 100 / Page 0 / Register 3-6: Reserved Register - 0x64 / 0x00 / 0x03-0x06 (B100_P0_R3-6)
14.5.5
Book 100 / Page 0 / Register 7: DSP Mute Register - 0x64 / 0x00 / 0x07 (B100_P0_R7)
14.5.6
Book 100 / Page 0 / Register 8-15: Reserved Register - 0x64 / 0x00 / 0x08-0x0F (B100_P0_R8-15)
14.5.7
Book 100 / Page 0 / Register 16: Interrupt 1 DSP Register - 0x64 / 0x00 / 0x10 (B100_P0_R16)
14.5.8
Book 100 / Page 0/ Register 17: Interrupt 2 DSP Register - 0x64 / 0x00 / 0x11 (B100_P0_R17)
14.5.9
Book 100 / Page 0 / Register 18: Condition 1 DSP Register - 0x64 / 0x00 / 0x12 (B100_P0_R18)
14.5.10
Book 100/ Page 0 / Register 19: Condition 2 DSP Register - 0x64 / 0x00 / 0x13 (B100_P0_R19)
14.5.11
Book 100 / Page 0 / Register 20: ISR and COND Control Register - 0x64 / 0x00 / 0x14 (B100_P0_R20)
14.5.12
Book 100 / Page 0/ Register 21: DSP Control Register - 0x64 / 0x00 / 0x15 (B100_P0_R21)
14.5.13
Book 100 / Page 0 / Register 22-26: Reserved Register - 0x64 / 0x00 / 0x16-0x1A (B100_P0_R22-26)
14.5.14
Book 100 / Page 0 / Register 27:PLL CLKIN Divider Register - 0x64 / 0x00 / 0x1B (B100_P0_R27)
14.5.15
Book 100 / Page 0 / Register 28:PLL J-VAL Divider Register - 0x64 / 0x00 / 0x1C (B100_P0_R28)
14.5.16
Book 100 / Page 0 / Register 29:PLL D-VAL Divider 2 Register - 0x64 / 0x00 / 0x1D (B100_P0_R29)
14.5.17
Book 100 / Page 0 / Register 30:PLL D-VAL Divider 1 Register - 0x64 / 0x00 / 0x1E (B100_P0_R30)
14.5.18
Book 100 / Page 0 / Register 31:DSP Clock Register - 0x64 / 0x00 / 0x1F (B100_P0_R31)
14.5.19
Book 100 / Page 0 / Register 32: N-VAL Divider Register - 0x64 / 0x00 / 0x20 (B100_P0_R32)
14.5.20
Book 100 / Page 0 / Register 33: MDAC-VAL Divider Register - 0x64 / 0x00 / 0x21 (B100_P0_R33)
14.5.21
Book 100 / Page 0 / Register 34: MADC-VAL Divider Register - 0x64 / 0x00 / 0x22 (B100_P0_R34)
14.5.22
Book 100 / Page 0 / Register 35-37: Reserved Register - 0x64 / 0x00 / 0x23-0x25 (B100_P0_R35-37)
14.5.23
Book 100 / Page 0 / Register 38: Charge-pump Clock Register - 0x64 / 0x00 / 0x26 (B100_P0_R38)
14.5.24
Book 100 / Page 0 / Register 39: Boost Clock Register - 0x64 / 0x00 / 0x27 (B100_P0_R39)
14.5.25
Book 100 / Page 0 / Register 40: Ramp Clock 1 Register - 0x64 / 0x00 / 0x28 (B100_P0_R40)
14.5.26
Book 100 / Page 0 / Register 41-42: Reserved Register - 0x64 / 0x00 / 0x29-0x2A (B100_P0_R41-42)
14.5.27
Book 100 / Page 0 / Register 43: Ramp Clock 2 Register - 0x64 / 0x00 / 0x2B (B100_P0_R43)
14.5.28
Book 100 / Page 0 / Register 44: Ramp Clock 3 Register - 0x64 / 0x00 / 0x2C (B100_P0_R44)
14.5.29
Book 100 / Page 0/ Register 45-126: Reserved Register - 0x64 / 0x01 / 0x2D-0x7E (B100_P0_R45-126)
14.5.30
Book 100 / Page 0 / Register 127: Book Selection Register - 0x64 / 0x00 / 0x7F (B100_P0_R127)
15
デバイスおよびドキュメントのサポート
15.1
ドキュメントのサポート
15.2
コミュニティ・リソース
15.3
商標
15.4
静電気放電に関する注意事項
15.5
Glossary
16
メカニカル、パッケージ、および注文情報
16.1
パッケージ寸法
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
YZ|42
サーマルパッド・メカニカル・データ
発注情報
jajsd19b_oa
jajsd19b_pm
14.3.44
Book 0 / Page 1 / Register 71-76: Reserved Registers - 0x00 / 0x01 / 0x47-0x4C (B0_P1_R71-76)
BIT
FIELD
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
RESERVED
R
xxxx xxxx
Reserved