JAJSD19 データシート

JAJSD19B August 2015 – February 2019 TAS2555

PRODUCTION DATA.

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

YZ|42

サーマルパッド・メカニカル・データ

発注情報

10.3.10.1.4 Clocking Faults

The TAS2555 device has two clock error detection blocks. The first is on the Audio Serial Interfaces (ASI). If a clock error is detected on the ASI interfaces audio artifacts can occur at the Class-D output. When enabled the ASI clock error detection can mute the device and shutdown the Class-D and DSP core. The clock error detection block is enabled by setting register bit B0_P0_R44[1]=1. The ASI1 or ASI2 clocks can be routed to the block for detection using register B0_P0_R44[4]. Additionally, the clock error can be routed to an interrupt pin and the sticky bit at register B0_P0_R104[5] indicates the clock error occurred. The second clock error detection block can monitor the DAC, ADC, and PLL clocks. When a clock error is detected the output is soft-muted and the Class-D powered down. This clock error detection is enabled using register bit B0_P0_R44[0], can be routed to interrupt pin and is indicated in the sticky bit B0_P0_R104[2].

When a clocking error occurs the following sequence should be performed to restart the device.

Clear the clock error interrupts by reading the sticky flags at registers B0_P0_R104 and B0_P0_R108
Disable the clock error detection blocks by writing B0_P0_R44[7:0]=0x00 as the internal dividers will be stopped on error detection.
Shutdown by writing B0_P0_R4=0x00 and B0_P0_R5=0x00
Re-power appropriate devices in the same registers
Re-enable the clock error detection blocks in register B0_P0_R44