JAJSCX9B November   2016  – February 2019 TAS2559

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  I2C Timing Requirements
    7. 8.7  SPI Timing Requirements
    8. 8.8  I2S/LJF/RJF Timing Requirements (Master Mode)
    9. 8.9  I2S/LJF/RJF Timing Requirements (Slave Mode)
    10. 8.10 DSP Timing Requirements (Master Mode)
    11. 8.11 DSP Timing Requirements (Slave Mode)
    12. 8.12 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  General I2C Operation
      2. 10.3.2  Single-Byte and Multiple-Byte Transfers
      3. 10.3.3  Single-Byte Write
      4. 10.3.4  Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 10.3.5  Single-Byte Read
      6. 10.3.6  Multiple-Byte Read
      7. 10.3.7  General SPI Operation
      8. 10.3.8  Class-D Edge Rate Control
      9. 10.3.9  IV Sense
      10. 10.3.10 Battery Tracking AGC
      11. 10.3.11 Boost Control
        1. 10.3.11.1 Boost Mode
        2. 10.3.11.2 Configurable Boost Current Limit (ILIM)
      12. 10.3.12 Thermal Fold-back
      13. 10.3.13 Fault Protection
        1. 10.3.13.1 Speaker Over-Current
        2. 10.3.13.2 Analog Under-Voltage
        3. 10.3.13.3 Die Over-Temperature
        4. 10.3.13.4 Clocking Faults
      14. 10.3.14 Brownout
      15. 10.3.15 Spread Spectrum vs Synchronized
      16. 10.3.16 IRQs and Flags
      17. 10.3.17 Software Reset
      18. 10.3.18 PurePath Console 3 Software TAS2559 Application
      19. 10.3.19 Operational Modes
        1. 10.3.19.1 Hardware Shutdown
        2. 10.3.19.2 Software Shutdown
        3. 10.3.19.3 Low Power Sleep
        4. 10.3.19.4 Software Reset
        5. 10.3.19.5 Device Processing Modes
          1. 10.3.19.5.1 Mode 1 - PCM input playback only
          2. 10.3.19.5.2 Mode 2 - PCM input playback + PCM IVsense output
          3. 10.3.19.5.3 Mode 3 - Smart Amp Mode
    4. 10.4 Device Functional Modes
      1. 10.4.1 Audio Digital I/O Interface
        1. 10.4.1.1 I2S Mode
        2. 10.4.1.2 DSP Mode
        3. 10.4.1.3 Right-Justified Mode (RJF)
        4. 10.4.1.4 Left-Justified Mode (LJF)
      2. 10.4.2 Mono PCM Mode
      3. 10.4.3 Stereo Application Example - TDM Mode
    5. 10.5 Programming
      1. 10.5.1 Code Loading and CRC check
      2. 10.5.2 Device Power Up and Unmute Sequence
      3. 10.5.3 Device Mute and Power Down Sequence
    6. 10.6 Register Map
      1. 10.6.1 Register Map Summary
        1. 10.6.1.1 Register Summary Table Book=0x00 Page=0x00
        2. 10.6.1.2 Register Summary Table Book=0x00 Page=0x01
        3. 10.6.1.3 Register Summary Table Book=0x00 Page=0x02
      2. 10.6.2 Register Maps
        1. 10.6.2.1   PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
          1. Table 23. Page Select Field Descriptions
        2. 10.6.2.2   RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
          1. Table 24. Software Reset Field Descriptions
        3. 10.6.2.3   POWER_1 (book=0x00 page=0x00 address=0x04) [reset=0h]
          1. Table 25. Power Up 1 Field Descriptions
        4. 10.6.2.4   POWER_2 (book=0x00 page=0x00 address=0x05) [reset=0h]
          1. Table 26. Power Up 2 Field Descriptions
        5. 10.6.2.5   SPK_GAIN_EDGE (book=0x00 page=0x00 address=0x06) [reset=0h]
          1. Table 27. Class-D Speaker Configuration Field Descriptions
        6. 10.6.2.6   MUTE (book=0x00 page=0x00 address=0x07) [reset=0h]
          1. Table 28. Mute Configuration Field Descriptions
        7. 10.6.2.7   SNS_CTRL (book=0x00 page=0x00 address=0x08) [reset=0h]
          1. Table 29. Sense Channel Control Field Descriptions
        8. 10.6.2.8   BOOST_CTRL_1 (book=0x00 page=0x00 address=0x09) [reset=0h]
          1. Table 30. Boost Control 1 Field Descriptions
        9. 10.6.2.9   SAR_CTRL_2 (book=0x00 page=0x00 address=0x14) [reset=32h]
          1. Table 31. SAR Control 2 Field Descriptions
        10. 10.6.2.10  SAR_CTRL_3 (book=0x00 page=0x00 address=0x15) [reset=4h]
          1. Table 32. SAR Control 3 Field Descriptions
        11. 10.6.2.11  SAR_VBAT_MSB (book=0x00 page=0x00 address=0x16) [reset=0h]
          1. Table 33. SAR VBAT Readback Field Descriptions
        12. 10.6.2.12  SAR_VBAT_LSB (book=0x00 page=0x00 address=0x17) [reset=0h]
          1. Table 34. SAR VBAT Readback Field Descriptions
        13. 10.6.2.13  SAR_VBST_MSB (book=0x00 page=0x00 address=0x18) [reset=0h]
          1. Table 35. SAR VBOOST Readback Field Descriptions
        14. 10.6.2.14  SAR_VBST_LSB (book=0x00 page=0x00 address=0x19) [reset=0h]
          1. Table 36. SAR VBOOST Readback Field Descriptions
        15. 10.6.2.15  SAR_TMP1_MSB (book=0x00 page=0x00 address=0x1A) [reset=0h]
          1. Table 37. SAR TEMP1 Readback Field Descriptions
        16. 10.6.2.16  SAR_TMP1_LSB (book=0x00 page=0x00 address=0x1B) [reset=0h]
          1. Table 38. SAR TEMP1 Readback Field Descriptions
        17. 10.6.2.17  SAR_TMP2_MSB (book=0x00 page=0x00 address=0x1C) [reset=0h]
          1. Table 39. SAR TEMP2 Readback Field Descriptions
        18. 10.6.2.18  SAR_TMP2_LSB (book=0x00 page=0x00 address=0x1D) [reset=0h]
          1. Table 40. SAR TEMP2 Readback Field Descriptions
        19. 10.6.2.19  CRC_CHECKSUM (book=0x00 page=0x00 address=0x20) [reset=0h]
          1. Table 41. Checksum Field Descriptions
        20. 10.6.2.20  CRC_RESET (book=0x00 page=0x00 address=0x21) [reset=0h]
          1. Table 42. Checksum Reset Field Descriptions
        21. 10.6.2.21  DSP_CTRL (book=0x00 page=0x00 address=0x22) [reset=1h]
          1. Table 43. DSP Control Field Descriptions
        22. 10.6.2.22  SSM_CTRL (book=0x00 page=0x00 address=0x28) [reset=0h]
          1. Table 44. Spread-Spectrum Control Field Descriptions
        23. 10.6.2.23  ASI_CTRL_1 (book=0x00 page=0x00 address=0x2A) [reset=0h]
          1. Table 45. ASI Control 1 Field Descriptions
        24. 10.6.2.24  BOOST_CTRL_2 (book=0x00 page=0x00 address=0x2B) [reset=3h]
          1. Table 46. Boost Control 1 Field Descriptions
        25. 10.6.2.25  CLOCK_CTRL_1 (book=0x00 page=0x00 address=0x2C) [reset=0h]
          1. Table 47. Clock Control 1 Field Descriptions
        26. 10.6.2.26  CLOCK_CTRL_2 (book=0x00 page=0x00 address=0x2D) [reset=17h]
          1. Table 48. Clock Control 2 Field Descriptions
        27. 10.6.2.27  CLOCK_CTRL_3 (book=0x00 page=0x00 address=0x2E) [reset=0h]
          1. Table 49. Clock Control 3 Field Descriptions
        28. 10.6.2.28  ASI_CTRL_2 (book=0x00 page=0x00 address=0x2F) [reset=0h]
          1. Table 50. ASI Control 2 Field Descriptions
        29. 10.6.2.29  CLOCK_CTRL_4 (book=0x00 page=0x00 address=0x32) [reset=0h]
          1. Table 51. Clock Control 4 Field Descriptions
        30. 10.6.2.30  DEBUG_1 (book=0x00 page=0x00 address=0x35) [reset=0h]
          1. Table 52. Debug Register 1 Field Descriptions
        31. 10.6.2.31  POWER_STATUS (book=0x00 page=0x00 address=0x64) [reset=0h]
          1. Table 53. Power Up Status Field Descriptions
        32. 10.6.2.32  DSP_BOOT_STATUS (book=0x00 page=0x00 address=0x65) [reset=0h]
          1. Table 54. DSP Boost Status Field Descriptions
        33. 10.6.2.33  INT_DET_1 (book=0x00 page=0x00 address=0x68) [reset=0h]
          1. Table 55. Interrupt Detected 1 Field Descriptions
        34. 10.6.2.34  INT_DET_2 (book=0x00 page=0x00 address=0x6C) [reset=0h]
          1. Table 56. Interrupt Detected 2 Field Descriptions
        35. 10.6.2.35  LOW_POWER (book=0x00 page=0x00 address=0x79) [reset=0h]
          1. Table 57. Lower Power Shutdown Field Descriptions
        36. 10.6.2.36  BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
          1. Table 58. Book Selection Field Descriptions
        37. 10.6.2.37  PAGE (book=0x00 page=0x01 address=0x00) [reset=1h]
          1. Table 59. Page Select Field Descriptions
        38. 10.6.2.38  ASI1_FORMAT (book=0x00 page=0x01 address=0x01) [reset=10h]
          1. Table 60. ASI1 Format Field Descriptions
        39. 10.6.2.39  ASI1_OFFSET_1 (book=0x00 page=0x01 address=0x03) [reset=0h]
          1. Table 61. ASI1 Offset Field Descriptions
        40. 10.6.2.40  ASI1_BUSKEEP (book=0x00 page=0x01 address=0x05) [reset=0h]
          1. Table 62. ASI1 Buskeeper Field Descriptions
        41. 10.6.2.41  ASI1_BCLK (book=0x00 page=0x01 address=0x08) [reset=0h]
          1. Table 63. ASI1 BCLK Field Descriptions
        42. 10.6.2.42  ASI1_WCLK (book=0x00 page=0x01 address=0x09) [reset=8h]
          1. Table 64. ASI1 WCLK Field Descriptions
        43. 10.6.2.43  ASI1_DIN_DOUT (book=0x00 page=0x01 address=0x0C) [reset=0h]
          1. Table 65. ASI1 DIN/DOUT Field Descriptions
        44. 10.6.2.44  ASI1_BDIV_CLK (book=0x00 page=0x01 address=0x0D) [reset=1h]
          1. Table 66. ASI1 BDIV Clock Field Descriptions
        45. 10.6.2.45  ASI1_BDIV_RATIO (book=0x00 page=0x01 address=0x0E) [reset=2h]
          1. Table 67. ASI1 BDIV Ratio Field Descriptions
        46. 10.6.2.46  ASI1_WDIV_RATIO (book=0x00 page=0x01 address=0x0F) [reset=20h]
          1. Table 68. ASI1 WDIV Ratio Field Descriptions
        47. 10.6.2.47  ASI1_CLK_OUT (book=0x00 page=0x01 address=0x10) [reset=0h]
          1. Table 69. ASI1 Clock Source Field Descriptions
        48. 10.6.2.48  ASI2_FORMAT (book=0x00 page=0x01 address=0x15) [reset=10h]
          1. Table 70. ASI2 Format Field Descriptions
        49. 10.6.2.49  ASI2_OFFSET_1 (book=0x00 page=0x01 address=0x17) [reset=0h]
          1. Table 71. ASI2 Offset Field Descriptions
        50. 10.6.2.50  ASI2_BUSKEEP (book=0x00 page=0x01 address=0x19) [reset=0h]
          1. Table 72. ASI2 Buskeeper Field Descriptions
        51. 10.6.2.51  ASI2_BCLK (book=0x00 page=0x01 address=0x1C) [reset=20h]
          1. Table 73. ASI2 BCLK Field Descriptions
        52. 10.6.2.52  ASI2_WCLK (book=0x00 page=0x01 address=0x1D) [reset=28h]
          1. Table 74. ASI2 WCLK Field Descriptions
        53. 10.6.2.53  ASI2_DIN_DOUT (book=0x00 page=0x01 address=0x20) [reset=38h]
          1. Table 75. ASI2 DIN/DOUT Field Descriptions
        54. 10.6.2.54  ASI2_BDIV_CLK (book=0x00 page=0x01 address=0x21) [reset=1h]
          1. Table 76. ASI2 BDIV Clock Field Descriptions
        55. 10.6.2.55  ASI2_BDIV_RATIO (book=0x00 page=0x01 address=0x22) [reset=2h]
          1. Table 77. ASI2 BDIV Ratio Field Descriptions
        56. 10.6.2.56  ASI2_WDIV_RATIO (book=0x00 page=0x01 address=0x23) [reset=20h]
          1. Table 78. ASI2 WDIV Ratio Field Descriptions
        57. 10.6.2.57  ASI2_CLK_OUT (book=0x00 page=0x01 address=0x24) [reset=33h]
          1. Table 79. ASI2 Clock Source Field Descriptions
        58. 10.6.2.58  GPIO1_PIN (book=0x00 page=0x01 address=0x3D) [reset=1h]
          1. Table 80. GPIO1 Field Descriptions
        59. 10.6.2.59  GPIO2_PIN (book=0x00 page=0x01 address=0x3E) [reset=1h]
          1. Table 81. GPIO2 Field Descriptions
        60. 10.6.2.60  GPIO3_PIN (book=0x00 page=0x01 address=0x3F) [reset=10h]
          1. Table 82. GPIO3 Field Descriptions
        61. 10.6.2.61  GPIO4_PIN (book=0x00 page=0x01 address=0x40) [reset=7h]
          1. Table 83. GPIO4 Field Descriptions
        62. 10.6.2.62  GPIO5_PIN (book=0x00 page=0x01 address=0x41) [reset=0h]
          1. Table 84. GPIO5 Field Descriptions
        63. 10.6.2.63  GPIO6_PIN (book=0x00 page=0x01 address=0x42) [reset=0h]
          1. Table 85. GPIO6 Field Descriptions
        64. 10.6.2.64  GPIO7_PIN (book=0x00 page=0x01 address=0x43) [reset=0h]
          1. Table 86. GPIO7 Field Descriptions
        65. 10.6.2.65  GPIO8_PIN (book=0x00 page=0x01 address=0x44) [reset=0h]
          1. Table 87. GPIO8 Field Descriptions
        66. 10.6.2.66  GPIO9_PIN (book=0x00 page=0x01 address=0x45) [reset=0h]
          1. Table 88. GPIO9 Field Descriptions
        67. 10.6.2.67  GPIO10_PIN (book=0x00 page=0x01 address=0x46) [reset=0h]
          1. Table 89. GPIO10 Field Descriptions
        68. 10.6.2.68  GPI_PIN (book=0x00 page=0x01 address=0x4D) [reset=0h]
          1. Table 90. GPI Pin Mode Field Descriptions
        69. 10.6.2.69  GPIO_HIZ_1 (book=0x00 page=0x01 address=0x4F) [reset=0h]
          1. Table 91. GPIO HiZ 1 Field Descriptions
        70. 10.6.2.70  GPIO_HIZ_2 (book=0x00 page=0x01 address=0x50) [reset=0h]
          1. Table 92. GPIO HiZ 2 Field Descriptions
        71. 10.6.2.71  GPIO_HIZ_3 (book=0x00 page=0x01 address=0x51) [reset=0h]
          1. Table 93. GPIO HiZ 3 Field Descriptions
        72. 10.6.2.72  GPIO_HIZ_4 (book=0x00 page=0x01 address=0x52) [reset=0h]
          1. Table 94. GPIO HiZ 4 Field Descriptions
        73. 10.6.2.73  GPIO_HIZ_5 (book=0x00 page=0x01 address=0x53) [reset=0h]
          1. Table 95. GPIO HiZ 5 Field Descriptions
        74. 10.6.2.74  BIT_BANG_OUT1 (book=0x00 page=0x01 address=0x58) [reset=0h]
          1. Table 96. Bit Bang Output 1 Field Descriptions
        75. 10.6.2.75  BIT_BANG_OUT2 (book=0x00 page=0x01 address=0x59) [reset=0h]
          1. Table 97. Bit Bang Output 2 Field Descriptions
        76. 10.6.2.76  BIT_BANG_IN1 (book=0x00 page=0x01 address=0x5A) [reset=0h]
          1. Table 98. Bit Bang Input 1 Field Descriptions
        77. 10.6.2.77  BIT_BANG_IN2 (book=0x00 page=0x01 address=0x5B) [reset=0h]
          1. Table 99. Bit Bang Input 2 Field Descriptions
        78. 10.6.2.78  BIT_BANG_IN3 (book=0x00 page=0x01 address=0x5C) [reset=0h]
          1. Table 100. Bit Bang Input 3 Field Descriptions
        79. 10.6.2.79  ASIM_BUSKEEP (book=0x00 page=0x01 address=0x60) [reset=0h]
          1. Table 101. ASIM Buskeeper Field Descriptions
        80. 10.6.2.80  ASIM_MODE (book=0x00 page=0x01 address=0x61) [reset=8h]
          1. Table 102. ASIM Mode Field Descriptions
        81. 10.6.2.81  ASIM_NUM_DEV (book=0x00 page=0x01 address=0x62) [reset=0h]
          1. Table 103. ASIM Number Devices Field Descriptions
        82. 10.6.2.82  ASIM_FORMAT (book=0x00 page=0x01 address=0x63) [reset=10h]
          1. Table 104. ASIM Format Field Descriptions
        83. 10.6.2.83  ASIM_BDIV_CLK (book=0x00 page=0x01 address=0x64) [reset=1h]
          1. Table 105. ASIM BDIV Clock Field Descriptions
        84. 10.6.2.84  ASIM_BDIV_RATIO (book=0x00 page=0x01 address=0x65) [reset=2h]
          1. Table 106. ASIM BDIV Ratio Field Descriptions
        85. 10.6.2.85  ASIM_WDIV_RATIO_1 (book=0x00 page=0x01 address=0x66) [reset=0h]
          1. Table 107. ASIM WDIV Ratio Field Descriptions
        86. 10.6.2.86  ASIM_WDIV_RATIO_2 (book=0x00 page=0x01 address=0x67) [reset=20h]
          1. Table 108. ASIM WDIV Ratio Field Descriptions
        87. 10.6.2.87  ASIM_BCLK (book=0x00 page=0x01 address=0x68) [reset=40h]
          1. Table 109. ASI1 BCLK Field Descriptions
        88. 10.6.2.88  ASIM_WCLK (book=0x00 page=0x01 address=0x69) [reset=38h]
          1. Table 110. ASI1 WCLK Field Descriptions
        89. 10.6.2.89  ASIM_DIN (book=0x00 page=0x01 address=0x6A) [reset=70h]
          1. Table 111. ASI1 DIN Field Descriptions
        90. 10.6.2.90  INT_GEN_1 (book=0x00 page=0x01 address=0x6C) [reset=0h]
          1. Table 112. Interrupt Generation 1 Field Descriptions
        91. 10.6.2.91  INT_GEN_2 (book=0x00 page=0x01 address=0x6D) [reset=0h]
          1. Table 113. Interrupt Generation 2 Field Descriptions
        92. 10.6.2.92  INT_GEN_3 (book=0x00 page=0x01 address=0x6E) [reset=0h]
          1. Table 114. Interrupt Generation 3 Field Descriptions
        93. 10.6.2.93  INT_GEN_4 (book=0x00 page=0x01 address=0x6F) [reset=0h]
          1. Table 115. Interrupt Generation 4 Field Descriptions
        94. 10.6.2.94  INT_GEN_5 (book=0x00 page=0x01 address=0x70) [reset=0h]
          1. Table 116. Interrupt Generation 5 Field Descriptions
        95. 10.6.2.95  INT_GEN_6 (book=0x00 page=0x01 address=0x71) [reset=0h]
          1. Table 117. Interrupt Generation 6 Field Descriptions
        96. 10.6.2.96  INT_IND_MODE (book=0x00 page=0x01 address=0x72) [reset=0h]
          1. Table 118. Interrupt Indication Mode Field Descriptions
        97. 10.6.2.97  MAIN_CLK_PIN (book=0x00 page=0x01 address=0x73) [reset=Dh]
          1. Table 119. Main Clock Source Field Descriptions
        98. 10.6.2.98  PLL_CLK_PIN (book=0x00 page=0x01 address=0x74) [reset=Dh]
          1. Table 120. PLL Clock Source Field Descriptions
        99. 10.6.2.99  CLKOUT_MUX (book=0x00 page=0x01 address=0x75) [reset=Dh]
          1. Table 121. CDIV_CLKIN Clock Source Field Descriptions
        100. 10.6.2.100 CLKOUT_CDIV_RATIO (book=0x00 page=0x01 address=0x76) [reset=1h]
          1. Table 122. CLKOUT CDIV Ratio Field Descriptions
        101. 10.6.2.101 I2C_MISC (book=0x00 page=0x01 address=0x7C) [reset=0h]
          1. Table 123. I2C Misc Field Descriptions
        102. 10.6.2.102 DEVICE_ID (book=0x00 page=0x01 address=0x7D) [reset=12h]
          1. Table 124. Device ID Field Descriptions
        103. 10.6.2.103 PAGE (book=0x00 page=0x02 address=0x00) [reset=1h]
          1. Table 125. Page Select Field Descriptions
        104. 10.6.2.104 RAMP_CTRL (book=0x00 page=0x02 address=0x06) [reset=0h]
          1. Table 126. Class-D Ramp Control Field Descriptions
        105. 10.6.2.105 PROTECTION_CFG (book=0x00 page=0x02 address=0x09) [reset=3h]
          1. Table 127. Configures the Devices Protection Blocks Field Descriptions
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Mono/Stereo Configuration
        2. 11.2.2.2 Boost Converter Passive Devices
        3. 11.2.2.3 EMI Passive Devices
        4. 11.2.2.4 Miscellaneous Passive Devices
      3. 11.2.3 Application Curve
    3. 11.3 Initialization Setup
  12. 12Power Supply Recommendations
    1. 12.1 Power Supplies
    2. 12.2 Power Supply Sequencing
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 ドキュメントのサポート
    2. 14.2 コミュニティ・リソース
    3. 14.3 商標
    4. 14.4 静電気放電に関する注意事項
    5. 14.5 Glossary
  15. 15メカニカル、パッケージ、および注文情報
    1. 15.1 パッケージ寸法

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • YZ|42
サーマルパッド・メカニカル・データ
発注情報

10.1 Overview

The TAS2559 device is a state-of-the-art Class-D audio amplifier which is a full system on a chip (SoC). The device features a ultra low-noise audio DAC and Class-D power amplifier which incorporates speaker voltage and current sensing feedback. An on-chip, low-latency DSP supports Texas Instruments' Smart Amp speaker protection algorithms to maximize loudness while maintaining safe speaker conditions. A smart integrated multi-level Class-H boost converter maximizes system efficiency at all times by tracking the required output voltage. The TAS2559 drives up to 3.8 W from a 4.2-V supply into an 8-Ω speaker with 1% THD, or up to up 5.7 W into a 4-Ω speaker with 1% THD.

The TAS2559 , with final processed digital output, can also be used to increase loudness and clarity in both Noise Canceling / Echo Cancelling speaker phone applications as well as for music or other sound applications. The TAS2559 accepts input audio data rates from 8 kHz to 96 kHz using ROM modes to fully support both speakerphone and music applications. When speaker protection system is running the maximum sampling rate is limited to 48 kHz.

The multi-level Class-H boost converter generates the Class-D amplifier supply rail. When the audio signal requires a output power below VBAT, the boost improves system efficiency by deactivating and connecting VBAT directly to the Class-D amplifier supply. When higher audio output power is required, the boost quickly activates and provides a much louder and clearer signal than can be achieved in any standard amplifier speaker system design approach. A boost inductor of 1uH can be used with a slight increase in boost ripple.

On-chip brownout detection system shutdown down audio at the user configurable threshold to avoid undesired system reset. In addition, an AGC can be selected to minimize clipping events when a lower power supply voltage is provided to the Class-D speaker driver. When this supply voltage drops below the proper level then under-voltage protection will be tripped. All protection statuses are available via register reads.

The Class-D output switching frequency is synchronous with the digital input audio sample rate to avoid left and right PWM frequency differences from beating in stereo applications. PWM Edge rate control and Spread Spectrum features are available if further EMI reduction is desired in the user’s system.

The interrupt request pin (IRQ) indicates a device error condition. The interrupt flag condition or conditions are selectable via I2C and include: thermal overload, Class-D over-current, VBAT level low, VBOOST level low, and PLL out-of-lock conditions. The IRQ signal is active-high for an interrupt request and low during normal operation. This behavior can be changed by a register setting to tri-state the pin during normal operation to allow the IRQ pin to be tied in parallel with other active-low interrupt request pins on other devices in the system.

Stereo configuration can be achieved with two TAS2559 devices by using the ADR0_SCLK and ADR1_MISO pins to set different I2C addresses in I2C mode or the SCL_SSZ chip enable pin in SPI mode. Refer to the General I2C Operation or General SPI Operation sections for more details.