SLASEI6A October   2019  – December 2019 TAS2564

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 TDM Port Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  PurePath™ Console 3 Software
      2. 8.3.2  Device Mode and Address Selection
      3. 8.3.3  General I2C Operation
      4. 8.3.4  Single-Byte and Multiple-Byte Transfers
      5. 8.3.5  Single-Byte Write
      6. 8.3.6  Multiple-Byte Write and Incremental Multiple-Byte Write
      7. 8.3.7  Single-Byte Read
      8. 8.3.8  Multiple-Byte Read
      9. 8.3.9  Register Organization
      10. 8.3.10 Operational Modes
        1. 8.3.10.1 Hardware Shutdown
        2. 8.3.10.2 Software Shutdown
        3. 8.3.10.3 Mute
        4. 8.3.10.4 Active
        5. 8.3.10.5 Perform Load Diagnostics
        6. 8.3.10.6 Mode Control and Software Reset
      11. 8.3.11 Faults and Status
      12. 8.3.12 Power Sequencing Requirements
      13. 8.3.13 Digital Input Pull Downs
    4. 8.4 Device Functional Modes
      1. 8.4.1  TDM Port
      2. 8.4.2  Playback Signal Path
        1. 8.4.2.1 High Pass Filter
        2. 8.4.2.2 Digital Volume Control and Amplifier Output Level
        3. 8.4.2.3 Auto-Mute During Idle Channel Mode
        4. 8.4.2.4 Auto-Start/Stop on Audio Clocks
        5. 8.4.2.5 Supply Tracking Limiters with Brown Out Prevention
        6. 8.4.2.6 Inter Chip Limiter Alignment
          1. 8.4.2.6.1 TDM Mode
        7. 8.4.2.7 Class-D Settings
      3. 8.4.3  SAR ADC
      4. 8.4.4  Boost
      5. 8.4.5  IV Sense
      6. 8.4.6  DC Detect
      7. 8.4.7  Load Diagnostics
      8. 8.4.8  Clocks and PLL
      9. 8.4.9  Thermal Foldback
      10. 8.4.10 Internal Tone Generator
    5. 8.5 Register Maps
      1. 8.5.1   Register Summary Table Page=0x00
      2. 8.5.2   Register Summary Table Page=0x01
      3. 8.5.3   Register Summary Table Page=0x02
      4. 8.5.4   Register Summary Table Page=0x03
      5. 8.5.5   Register Summary Table Page=0x04
      6. 8.5.6   PAGE0 (page=0x00 address=0x00) [reset=0h]
        1. Table 116. Device Page Field Descriptions
      7. 8.5.7   SW_RESET (page=0x00 address=0x01) [reset=1h]
        1. Table 117. Software Reset Field Descriptions
      8. 8.5.8   PWR_CTL (page=0x00 address=0x02) [reset=8Eh]
        1. Table 118. Power Control Field Descriptions
      9. 8.5.9   PB_CFG1 (page=0x00 address=0x03) [reset=20h]
        1. Table 119. Playback Configuration 1 Field Descriptions
      10. 8.5.10  MISC_CFG1 (page=0x00 address=0x04) [reset=C6h]
        1. Table 120. Misc Configuration 1 Field Descriptions
      11. 8.5.11  MISC_CFG2 (page=0x00 address=0x05) [reset=22h]
        1. Table 121. Misc Configuration 2 Field Descriptions
      12. 8.5.12  TDM_CFG0 (page=0x00 address=0x06) [reset=9h]
        1. Table 122. TDM Configuration 0 Field Descriptions
      13. 8.5.13  TDM_CFG1 (page=0x00 address=0x07) [reset=2h]
        1. Table 123. TDM Configuration 1 Field Descriptions
      14. 8.5.14  TDM_CFG2 (page=0x00 address=0x08) [reset=Ah]
        1. Table 124. TDM Configuration 2 Field Descriptions
      15. 8.5.15  TDM_CFG3 (page=0x00 address=0x09) [reset=10h]
        1. Table 125. TDM Configuration 3 Field Descriptions
      16. 8.5.16  TDM_CFG4 (page=0x00 address=0x0A) [reset=13h]
        1. Table 126. TDM Configuration 4 Field Descriptions
      17. 8.5.17  TDM_CFG5 (page=0x00 address=0x0B) [reset=2h]
        1. Table 127. TDM Configuration 5 Field Descriptions
      18. 8.5.18  TDM_CFG6 (page=0x00 address=0x0C) [reset=0h]
        1. Table 128. TDM Configuration 6 Field Descriptions
      19. 8.5.19  TDM_CFG7 (page=0x00 address=0x0D) [reset=4h]
        1. Table 129. TDM Configuration 7 Field Descriptions
      20. 8.5.20  TDM_CFG8 (page=0x00 address=0x0E) [reset=5h]
        1. Table 130. TDM Configuration 8 Field Descriptions
      21. 8.5.21  TDM_CFG9 (page=0x00 address=0x0F) [reset=6h]
        1. Table 131. TDM Configuration 9 Field Descriptions
      22. 8.5.22  TDM_CFG10 (page=0x00 address=0x10) [reset=7h]
        1. Table 132. TDM Configuration 10 Field Descriptions
      23. 8.5.23  TDM_DET (page=0x00 address=0x11) [reset=7Fh]
        1. Table 133. TDM Clock detection monitor Field Descriptions
      24. 8.5.24  LIM_CFG_0 (page=0x00 address=0x12) [reset=12h]
        1. Table 134. Limiter Configuration 0 Field Descriptions
      25. 8.5.25  LIM_CFG_1 (page=0x00 address=0x13) [reset=76h]
        1. Table 135. Limiter Configuration 1 Field Descriptions
      26. 8.5.26  BOP_CFG_0 (page=0x00 address=0x14) [reset=1h]
        1. Table 136. Brown Out Prevention 0 Field Descriptions
      27. 8.5.27  BOP_CFG_1 (page=0x00 address=0x15) [reset=2Eh]
        1. Table 137. Brown Out Prevention 1 Field Descriptions
      28. 8.5.28  GAIN_ICLA_CFG0 (page=0x00 address=0x18) [reset=Ch]
        1. Table 138. Inter Chip Limiter Alignment 0 Field Descriptions
      29. 8.5.29  ICLA_CFG1 (page=0x00 address=0x19) [reset=0h]
        1. Table 139. Inter Chip Limiter Alignment 1 Field Descriptions
      30. 8.5.30  INT_MASK0 (page=0x00 address=0x1A) [reset=FCh]
        1. Table 140. Interrupt Mask 0 Field Descriptions
      31. 8.5.31  INT_MASK1 (page=0x00 address=0x1B) [reset=A6h]
        1. Table 141. Interrupt Mask 1 Field Descriptions
      32. 8.5.32  INT_MASK6 (page=0x00 address=0x1E) [reset=80h]
        1. Table 142. Interrupt Mask 6- Interrupt masks. Field Descriptions
      33. 8.5.33  INT_LTCH0 (page=0x00 address=0x24) [reset=0h]
        1. Table 143. Latched Interrupt Readback 0 Field Descriptions
      34. 8.5.34  INT_LTCH1 (page=0x00 address=0x25) [reset=0h]
        1. Table 144. Latched Interrupt Readback 1 Field Descriptions
      35. 8.5.35  INT_LTCH6 (page=0x00 address=0x28) [reset=0h]
        1. Table 145. Latched Interrupt Readback 6 Field Descriptions
      36. 8.5.36  VBAT_MSB (page=0x00 address=0x2A) [reset=0h]
        1. Table 146. SAR ADC Conversion 0 Field Descriptions
      37. 8.5.37  VBAT_LSB (page=0x00 address=0x2B) [reset=0h]
        1. Table 147. SAR ADC Conversion 1 Field Descriptions
      38. 8.5.38  TEMP (page=0x00 address=0x2C) [reset=0h]
        1. Table 148. SAR ADC Conversion 2 Field Descriptions
      39. 8.5.39  INT_CLK (page=0x00 address=0x30) [reset=19h]
        1. Table 149. Interrupt and Clock Error Field Descriptions
      40. 8.5.40  DIN_PD (page=0x00 address=0x31) [reset=40h]
        1. Table 150. Digital Input Pin Pull Down Field Descriptions
      41. 8.5.41  MISC_CFG3 (page=0x00 address=0x32) [reset=80h]
        1. Table 151. Misc Configuration 3 Field Descriptions
      42. 8.5.42  BOOST_CFG1 (page=0x00 address=0x33) [reset=34h]
        1. Table 152. Boost Configure 1 Field Descriptions
      43. 8.5.43  BOOST_CFG2 (page=0x00 address=0x34) [reset=40h]
        1. Table 153. Boost Configure 2 Field Descriptions
      44. 8.5.44  BOOST_CFG3 (page=0x00 address=0x35) [reset=78h]
        1. Table 154. Boost Configure 3 Field Descriptions
      45. 8.5.45  MISC_CFG4 (page=0x00 address=0x3D) [reset=8h]
        1. Table 155. Misc Configuration 4 Field Descriptions
      46. 8.5.46  TG_CFG0 (page=0x00 address=0x3F) [reset=0h]
        1. Table 156. Tone Generator Field Descriptions
      47. 8.5.47  BOOST_CFG4 (page=0x00 address=0x40) [reset=79h]
        1. Table 157. Boost Configure 4 Field Descriptions
      48. 8.5.48  TDM_CFG11 (page=0x00 address=0x41) [reset=48h]
        1. Table 158. TDM Configuration 11 Field Descriptions
      49. 8.5.49  IO_DRV1 (page=0x00 address=0x42) [reset=0h]
        1. Table 159. PAD drain strength control 1 Field Descriptions
      50. 8.5.50  IO_DRV2 (page=0x00 address=0x43) [reset=0h]
        1. Table 160. PAD drain strength control 2 Field Descriptions
      51. 8.5.51  IO_DRV3 (page=0x00 address=0x44) [reset=0h]
        1. Table 161. PAD drain strength control 3 Field Descriptions
      52. 8.5.52  MISC_CFG5 (page=0x00 address=0x48) [reset=A0h]
        1. Table 162. Boost and Class-D Settings Field Descriptions
      53. 8.5.53  REV_ID (page=0x00 address=0x7D) [reset=0h]
        1. Table 163. Revision and PG ID Field Descriptions
      54. 8.5.54  I2C_CKSUM (page=0x00 address=0x7E) [reset=0h]
        1. Table 164. I2C Checksum Field Descriptions
      55. 8.5.55  BOOK (page=0x00 address=0x7F) [reset=0h]
        1. Table 165. Device Book Field Descriptions
      56. 8.5.56  PAGE1 (page=0x01 address=0x00) [reset=0h]
        1. Table 166. Device Page Field Descriptions
      57. 8.5.57  TF_CFG (page=0x01 address=0x08) [reset=0h]
        1. Table 167. Thermal Folder Configure Field Descriptions
      58. 8.5.58  LDG_CFG2 (page=0x01 address=0x24) [reset=0h]
        1. Table 168. Load Diagnostic 1 Field Descriptions
      59. 8.5.59  PAGE2 (page=0x02 address=0x00) [reset=0h]
        1. Table 169. Device Page Field Descriptions
      60. 8.5.60  DVC_CFG1 (page=0x02 address=0x0C) [reset=40h]
        1. Table 170. Digital Volume Control 1 Field Descriptions
      61. 8.5.61  DVC_CFG2 (page=0x02 address=0x0D) [reset=0h]
        1. Table 171. Digital Volume Control 2 Field Descriptions
      62. 8.5.62  DVC_CFG3 (page=0x02 address=0x0E) [reset=0h]
        1. Table 172. Digital Volume Control 3 Field Descriptions
      63. 8.5.63  DVC_CFG4 (page=0x02 address=0x0F) [reset=0h]
        1. Table 173. Digital Volume Control 4 Field Descriptions
      64. 8.5.64  DVC_CFG5 (page=0x02 address=0x10) [reset=3h]
        1. Table 174. Digital Volume Control 5 Field Descriptions
      65. 8.5.65  DVC_CFG6 (page=0x02 address=0x11) [reset=4Ah]
        1. Table 175. Digital Volume Control 6 Field Descriptions
      66. 8.5.66  DVC_CFG7 (page=0x02 address=0x12) [reset=51h]
        1. Table 176. Digital Volume Control 7 Field Descriptions
      67. 8.5.67  DVC_CFG8 (page=0x02 address=0x13) [reset=6Ch]
        1. Table 177. Digital Volume Control 8 Field Descriptions
      68. 8.5.68  LIM_CFG1 (page=0x02 address=0x14) [reset=2Dh]
        1. Table 178. Limiter Configuration 1 Field Descriptions
      69. 8.5.69  LIM_CFG2 (page=0x02 address=0x15) [reset=6Ah]
        1. Table 179. Limiter Configuration 2- Sets limiter max attenuation Field Descriptions
      70. 8.5.70  LIM_CFG3 (page=0x02 address=0x16) [reset=86h]
        1. Table 180. Limiter Configuration 3- Sets limiter max attenuation Field Descriptions
      71. 8.5.71  LIM_CFG4 (page=0x02 address=0x17) [reset=6Fh]
        1. Table 181. Limiter Configuration 4- Sets limiter max attenuation Field Descriptions
      72. 8.5.72  LIM_CFG5 (page=0x02 address=0x18) [reset=56h]
        1. Table 182. Limiter Configuration 5 Field Descriptions
      73. 8.5.73  LIM_CFG6 (page=0x02 address=0x19) [reset=B7h]
        1. Table 183. Limiter Configuration 6 Field Descriptions
      74. 8.5.74  LIM_CFG7 (page=0x02 address=0x1A) [reset=96h]
        1. Table 184. Limiter Configuration 7 Field Descriptions
      75. 8.5.75  LIM_CFG8 (page=0x02 address=0x1B) [reset=FFh]
        1. Table 185. Limiter Configuration 8 Field Descriptions
      76. 8.5.76  LIM_CFG9 (page=0x02 address=0x1C) [reset=16h]
        1. Table 186. Limiter Configuration 9 Field Descriptions
      77. 8.5.77  LIM_CFG10 (page=0x02 address=0x1D) [reset=66h]
        1. Table 187. Limiter Configuration 10 Field Descriptions
      78. 8.5.78  LIM_CFG11 (page=0x02 address=0x1E) [reset=66h]
        1. Table 188. Limiter Configuration 11 Field Descriptions
      79. 8.5.79  LIM_CFG12 (page=0x02 address=0x1F) [reset=66h]
        1. Table 189. Limiter Configuration 12 Field Descriptions
      80. 8.5.80  LIM_CFG13 (page=0x02 address=0x20) [reset=34h]
        1. Table 190. Limiter Configuration 13 Field Descriptions
      81. 8.5.81  LIM_CFG14 (page=0x02 address=0x21) [reset=CCh]
        1. Table 191. Limiter Configuration 14 Field Descriptions
      82. 8.5.82  LIM_CFG15 (page=0x02 address=0x22) [reset=CCh]
        1. Table 192. Limiter Configuration 15 Field Descriptions
      83. 8.5.83  LIM_CFG16 (page=0x02 address=0x23) [reset=CDh]
        1. Table 193. Limiter Configuration 16 Field Descriptions
      84. 8.5.84  LIM_CFG17 (page=0x02 address=0x24) [reset=10h]
        1. Table 194. Limiter Configuration 1 Field Descriptions
      85. 8.5.85  LIM_CFG18 (page=0x02 address=0x25) [reset=0h]
        1. Table 195. Limiter Configuration 2 Field Descriptions
      86. 8.5.86  LIM_CFG19 (page=0x02 address=0x26) [reset=0h]
        1. Table 196. Limiter Configuration 3 Field Descriptions
      87. 8.5.87  LIM_CFG20 (page=0x02 address=0x27) [reset=0h]
        1. Table 197. Limiter Configuration 4 Field Descriptions
      88. 8.5.88  BOP_CFG1 (page=0x02 address=0x28) [reset=2Eh]
        1. Table 198. Brown Out Prevention 1 Field Descriptions
      89. 8.5.89  BOP_CFG2 (page=0x02 address=0x29) [reset=66h]
        1. Table 199. Brown Out Prevention 2 Field Descriptions
      90. 8.5.90  BOP_CFG3 (page=0x02 address=0x2A) [reset=66h]
        1. Table 200. Brown Out Prevention 3 Field Descriptions
      91. 8.5.91  BOP_CFG4 (page=0x02 address=0x2B) [reset=66h]
        1. Table 201. Brown Out Prevention 4 Field Descriptions
      92. 8.5.92  BOP_CFG5 (page=0x02 address=0x2C) [reset=2Bh]
        1. Table 202. Brown Out Prevention 5 Field Descriptions
      93. 8.5.93  BOP_CFG6 (page=0x02 address=0x2D) [reset=33h]
        1. Table 203. Brown Out Prevention 6 Field Descriptions
      94. 8.5.94  BOP_CFG7 (page=0x02 address=0x2E) [reset=33h]
        1. Table 204. Brown Out Prevention 7 Field Descriptions
      95. 8.5.95  BOP_CFG8 (page=0x02 address=0x2F) [reset=33h]
        1. Table 205. Brown Out Prevention 8 Field Descriptions
      96. 8.5.96  HPFC_CFG1 (page=0x02 address=0x30) [reset=7Fh]
        1. Table 206. HPF Coefficient 1 Field Descriptions
      97. 8.5.97  HPFC_CFG2 (page=0x02 address=0x31) [reset=FBh]
        1. Table 207. HPF Coefficient 2 Field Descriptions
      98. 8.5.98  HPFC_CFG3 (page=0x02 address=0x32) [reset=B6h]
        1. Table 208. HPF Coefficient 3 Field Descriptions
      99. 8.5.99  HPFC_CFG4 (page=0x02 address=0x33) [reset=14h]
        1. Table 209. HPF Coefficient 4 Field Descriptions
      100. 8.5.100 HPFC_CFG5 (page=0x02 address=0x34) [reset=80h]
        1. Table 210. HPF Coefficient 5 Field Descriptions
      101. 8.5.101 HPFC_CFG6 (page=0x02 address=0x35) [reset=4h]
        1. Table 211. HPF Coefficient 6 Field Descriptions
      102. 8.5.102 HPFC_CFG7 (page=0x02 address=0x36) [reset=49h]
        1. Table 212. HPF Coefficient 7 Field Descriptions
      103. 8.5.103 HPFC_CFG8 (page=0x02 address=0x37) [reset=ECh]
        1. Table 213. HPF Coefficient 8 Field Descriptions
      104. 8.5.104 HPFC_CFG9 (page=0x02 address=0x38) [reset=7Fh]
        1. Table 214. HPF Coefficient 9 Field Descriptions
      105. 8.5.105 HPFC_CFG10 (page=0x02 address=0x39) [reset=7Fh]
        1. Table 215. HPF Coefficient 10 Field Descriptions
      106. 8.5.106 HPFC_CFG11 (page=0x02 address=0x3A) [reset=6Ch]
        1. Table 216. HPF Coefficient 11 Field Descriptions
      107. 8.5.107 HPFC_CFG12 (page=0x02 address=0x3B) [reset=28h]
        1. Table 217. HPF Coefficient 12 Field Descriptions
      108. 8.5.108 TG_CFG1 (page=0x02 address=0x3C) [reset=3Fh]
        1. Table 218. Tone Generator 1 Freq Calc 1 Field Descriptions
      109. 8.5.109 TG_CFG2 (page=0x02 address=0x3D) [reset=FFh]
        1. Table 219. Tone Generator 1 Freq Calc 1 Field Descriptions
      110. 8.5.110 TG_CFG3 (page=0x02 address=0x3E) [reset=7Ah]
        1. Table 220. Tone Generator 1 Freq Calc 1 Field Descriptions
      111. 8.5.111 TG_CFG4 (page=0x02 address=0x3F) [reset=E3h]
        1. Table 221. Tone Generator 1 Freq Calc 1 Field Descriptions
      112. 8.5.112 TG_CFG5 (page=0x02 address=0x40) [reset=1h]
        1. Table 222. Tone Generator 1 Freq Calc 2 Field Descriptions
      113. 8.5.113 TG_CFG6 (page=0x02 address=0x41) [reset=1h]
        1. Table 223. Tone Generator 1 Freq Calc 2 Field Descriptions
      114. 8.5.114 TG_CFG7 (page=0x02 address=0x42) [reset=5Bh]
        1. Table 224. Tone Generator 1 Freq Calc 2 Field Descriptions
      115. 8.5.115 TG_CFG8 (page=0x02 address=0x43) [reset=4Ch]
        1. Table 225. Tone Generator 1 Freq Calc 2 Field Descriptions
      116. 8.5.116 TG_CFG9 (page=0x02 address=0x44) [reset=0h]
        1. Table 226. Tone Generator 1 Freq Calc 3 Field Descriptions
      117. 8.5.117 TG_CFG10 (page=0x02 address=0x45) [reset=0h]
        1. Table 227. Tone Generator 1 Freq Calc 3 Field Descriptions
      118. 8.5.118 TG_CFG11 (page=0x02 address=0x46) [reset=3h]
        1. Table 228. Tone Generator 1 Freq Calc 3 Field Descriptions
      119. 8.5.119 TG_CFG12 (page=0x02 address=0x47) [reset=1Fh]
        1. Table 229. Tone Generator 1 Freq Calc 3 Field Descriptions
      120. 8.5.120 TG_CFG13 (page=0x02 address=0x48) [reset=2h]
        1. Table 230. Tone Generator 1 Amplitude Calc Field Descriptions
      121. 8.5.121 TG_CFG14 (page=0x02 address=0x49) [reset=46h]
        1. Table 231. Tone Generator 1 Amplitude Calc Field Descriptions
      122. 8.5.122 TG_CFG15 (page=0x02 address=0x4A) [reset=B4h]
        1. Table 232. Tone Generator 1 Amplitude Calc Field Descriptions
      123. 8.5.123 TG_CFG16 (page=0x02 address=0x4B) [reset=E4h]
        1. Table 233. Tone Generator 1 Amplitude Calc Field Descriptions
      124. 8.5.124 LD_CFG0 (page=0x02 address=0x5C) [reset=2h]
        1. Table 234. Load Diagnostics Resistance Upper Threshold Field Descriptions
      125. 8.5.125 LD_CFG1 (page=0x02 address=0x5D) [reset=80h]
        1. Table 235. Load Diagnostics Resistance Upper Threshold Field Descriptions
      126. 8.5.126 LD_CFG2 (page=0x02 address=0x5E) [reset=0h]
        1. Table 236. Load Diagnostics Resistance Upper Threshold Field Descriptions
      127. 8.5.127 LD_CFG3 (page=0x02 address=0x5F) [reset=0h]
        1. Table 237. Load Diagnostics Resistance Upper Threshold Field Descriptions
      128. 8.5.128 LD_CFG4 (page=0x02 address=0x60) [reset=0h]
        1. Table 238. Load Diagnostics Resistance Lower Threshold Field Descriptions
      129. 8.5.129 LD_CFG5 (page=0x02 address=0x61) [reset=19h]
        1. Table 239. Load Diagnostics Resistance Lower Threshold Field Descriptions
      130. 8.5.130 LD_CFG6 (page=0x02 address=0x62) [reset=99h]
        1. Table 240. Load Diagnostics Resistance Lower Threshold Field Descriptions
      131. 8.5.131 LD_CFG7 (page=0x02 address=0x63) [reset=9Ah]
        1. Table 241. Load Diagnostics Resistance Lower Threshold Field Descriptions
      132. 8.5.132 IDC_CFG0 (page=0x02 address=0x64) [reset=0h]
        1. Table 242. Idle channel detection threshold Field Descriptions
      133. 8.5.133 IDC_CFG1 (page=0x02 address=0x65) [reset=20h]
        1. Table 243. Idle channel detection threshold Field Descriptions
      134. 8.5.134 IDC_CFG2 (page=0x02 address=0x66) [reset=C4h]
        1. Table 244. Idle channel detection threshold Field Descriptions
      135. 8.5.135 IDC_CFG3 (page=0x02 address=0x67) [reset=9Ch]
        1. Table 245. Idle channel detection threshold Field Descriptions
      136. 8.5.136 IDC_CFG4 (page=0x02 address=0x68) [reset=2h]
        1. Table 246. MID Power Threshold Field Descriptions
      137. 8.5.137 IDC_CFG5 (page=0x02 address=0x69) [reset=46h]
        1. Table 247. MID Power Threshold Field Descriptions
      138. 8.5.138 IDC_CFG6 (page=0x02 address=0x6A) [reset=B4h]
        1. Table 248. MID Power Threshold Field Descriptions
      139. 8.5.139 IDC_CFG7 (page=0x02 address=0x6B) [reset=E4h]
        1. Table 249. MID Power Threshold Field Descriptions
      140. 8.5.140 IDC_CFG8 (page=0x02 address=0x6C) [reset=0h]
        1. Table 250. Hystersis for idle channel detection Field Descriptions
      141. 8.5.141 IDC_CFG9 (page=0x02 address=0x6D) [reset=0h]
        1. Table 251. Hystersis for idle channel detection Field Descriptions
      142. 8.5.142 IDC_CFG10 (page=0x02 address=0x6E) [reset=12h]
        1. Table 252. Hystersis for idle channel detection Field Descriptions
      143. 8.5.143 IDC_CFG11 (page=0x02 address=0x6F) [reset=C0h]
        1. Table 253. Hystersis for idle channel detection Field Descriptions
      144. 8.5.144 IVHPFC_CFG1 (page=0x02 address=0x70) [reset=7Fh]
        1. Table 254. IVSENSE HPF N0 coefficient Field Descriptions
      145. 8.5.145 IVHPFC_CFG2 (page=0x02 address=0x71) [reset=FBh]
        1. Table 255. IVSENSE HPF N0 coefficient Field Descriptions
      146. 8.5.146 IVHPFC_CFG3 (page=0x02 address=0x72) [reset=B6h]
        1. Table 256. IVSENSE HPF N0 coefficient Field Descriptions
      147. 8.5.147 IVHPFC_CFG4 (page=0x02 address=0x73) [reset=14h]
        1. Table 257. IVSENSE HPF N0 coefficient Field Descriptions
      148. 8.5.148 IVHPFC_CFG5 (page=0x02 address=0x74) [reset=80h]
        1. Table 258. IVSENSE HPF N1 coefficient Field Descriptions
      149. 8.5.149 IVHPFC_CFG6 (page=0x02 address=0x75) [reset=4h]
        1. Table 259. IVSENSE HPF N1 coefficient Field Descriptions
      150. 8.5.150 IVHPFC_CFG7 (page=0x02 address=0x76) [reset=49h]
        1. Table 260. IVSENSE HPF N1 coefficient Field Descriptions
      151. 8.5.151 IVHPFC_CFG8 (page=0x02 address=0x77) [reset=ECh]
        1. Table 261. IVSENSE HPF N1 coefficient Field Descriptions
      152. 8.5.152 IVHPFC_CFG9 (page=0x02 address=0x78) [reset=7Fh]
        1. Table 262. IVSENSE HPF D1 coefficient Field Descriptions
      153. 8.5.153 IVHPFC_CFG10 (page=0x02 address=0x79) [reset=F7h]
        1. Table 263. IVSENSE HPF D1 coefficient Field Descriptions
      154. 8.5.154 IVHPFC_CFG11 (page=0x02 address=0x7A) [reset=6Ch]
        1. Table 264. IVSENSE HPF D1 coefficient Field Descriptions
      155. 8.5.155 IVHPFC_CFG12 (page=0x02 address=0x7B) [reset=28h]
        1. Table 265. IVSENSE HPF D1 coefficient Field Descriptions
      156. 8.5.156 TF_CFG_1 (page=0x02 address=0x7C) [reset=72h]
        1. Table 266. Thermal foldback limiter slope (in db/C) Field Descriptions
      157. 8.5.157 TF_CFG_2 (page=0x02 address=0x7D) [reset=14h]
        1. Table 267. Thermal foldback limiter slope (in db/C) Field Descriptions
      158. 8.5.158 TF_CFG_3 (page=0x02 address=0x7E) [reset=82h]
        1. Table 268. Thermal foldback limiter slope (in db/C) Field Descriptions
      159. 8.5.159 TF_CFG_4 (page=0x02 address=0x7F) [reset=C0h]
        1. Table 269. Thermal foldback limiter slope (in db/C) Field Descriptions
      160. 8.5.160 PAGE3 (page=0x03 address=0x00) [reset=0h]
        1. Table 270. Device Page Field Descriptions
      161. 8.5.161 DC_DET_THR1 (page=0x03 address=0x1C) [reset=18h]
        1. Table 271. DC detection threshold 1 Field Descriptions
      162. 8.5.162 DC_DET_THR2 (page=0x03 address=0x1D) [reset=2Ah]
        1. Table 272. DC detection threshold 2 Field Descriptions
      163. 8.5.163 DC_DET_THR3 (page=0x03 address=0x1E) [reset=FFh]
        1. Table 273. DC detection threshold 3 Field Descriptions
      164. 8.5.164 DC_DET_THR4 (page=0x03 address=0x1F) [reset=53h]
        1. Table 274. DC detection threshold 4 Field Descriptions
      165. 8.5.165 DC_DET_HYST1 (page=0x03 address=0x20) [reset=0h]
        1. Table 275. DC detection hysteresis time 1 Field Descriptions
      166. 8.5.166 DC_DET_HYST2 (page=0x03 address=0x21) [reset=0h]
        1. Table 276. DC detection hysteresis time 2 Field Descriptions
      167. 8.5.167 DC_DET_HYST3 (page=0x03 address=0x22) [reset=27h]
        1. Table 277. DC detection hysteresis time 3 Field Descriptions
      168. 8.5.168 DC_DET_HYST4 (page=0x03 address=0x23) [reset=10h]
        1. Table 278. DC detection hysteresis time 4 Field Descriptions
      169. 8.5.169 CLS_H_CFG1 (page=0x03 address=0x24) [reset=Ah]
        1. Table 279. ClassH Field Descriptions
      170. 8.5.170 CLS_H_CFG2 (page=0x03 address=0x25) [reset=3Bh]
        1. Table 280. ClassH Field Descriptions
      171. 8.5.171 CLS_H_CFG3 (page=0x03 address=0x26) [reset=C7h]
        1. Table 281. ClassH Field Descriptions
      172. 8.5.172 CLS_H_CFG4 (page=0x03 address=0x27) [reset=DCh]
        1. Table 282. ClassH Field Descriptions
      173. 8.5.173 CLS_H_CFG5 (page=0x03 address=0x28) [reset=0h]
        1. Table 283. ClassH Field Descriptions
      174. 8.5.174 CLS_H_CFG6 (page=0x03 address=0x29) [reset=0h]
        1. Table 284. ClassH Field Descriptions
      175. 8.5.175 CLS_H_CFG7 (page=0x03 address=0x2A) [reset=0h]
        1. Table 285. ClassH Field Descriptions
      176. 8.5.176 CLS_H_CFG8 (page=0x03 address=0x2B) [reset=0h]
        1. Table 286. ClassH Field Descriptions
      177. 8.5.177 CLS_H_CFG9 (page=0x03 address=0x74) [reset=0h]
        1. Table 287. ClassH Minimum boost level in Voltage Field Descriptions
      178. 8.5.178 CLS_H_CFG10 (page=0x03 address=0x75) [reset=0h]
        1. Table 288. ClassH Minimum boost level in Voltage Field Descriptions
      179. 8.5.179 CLS_H_CFG11 (page=0x03 address=0x76) [reset=2h]
        1. Table 289. ClassH Minimum boost level in Voltage Field Descriptions
      180. 8.5.180 CLS_H_CFG12 (page=0x03 address=0x77) [reset=0h]
        1. Table 290. ClassH Minimum boost level in Voltage Field Descriptions
      181. 8.5.181 PAGE4 (page=0x04 address=0x00) [reset=0h]
        1. Table 291. Device Page Field Descriptions
      182. 8.5.182 LD_CFG8 (page=0x04 address=0x18) [reset=0h]
        1. Table 292. Load Resistance Value after load diagnostics is completed Field Descriptions
      183. 8.5.183 LD_CFG9 (page=0x04 address=0x19) [reset=0h]
        1. Table 293. Load Resistance Value after load diagnostics is completed Field Descriptions
      184. 8.5.184 LD_CFG10 (page=0x04 address=0x1A) [reset=0h]
        1. Table 294. Load Resistance Value after load diagnostics is completed Field Descriptions
      185. 8.5.185 LD_CFG11 (page=0x04 address=0x1B) [reset=0h]
        1. Table 295. Load Resistance Value after load diagnostics is completed Field Descriptions
      186. 8.5.186 TF_CFG4 (page=0x04 address=0x58) [reset=0h]
        1. Table 296. Thermal foldback hold count (samples) Field Descriptions
      187. 8.5.187 TF_CFG5 (page=0x04 address=0x59) [reset=0h]
        1. Table 297. Thermal foldback hold count (samples) Field Descriptions
      188. 8.5.188 TF_CFG6 (page=0x04 address=0x5A) [reset=0h]
        1. Table 298. Thermal foldback hold count (samples) Field Descriptions
      189. 8.5.189 TF_CFG7 (page=0x04 address=0x5B) [reset=64h]
        1. Table 299. Thermal foldback hold count (samples) Field Descriptions
      190. 8.5.190 TF_CFG8 (page=0x04 address=0x5C) [reset=40h]
        1. Table 300. Thermal foldback limiter release rate (db/samples) Field Descriptions
      191. 8.5.191 TF_CFG9 (page=0x04 address=0x5D) [reset=BDh]
        1. Table 301. Thermal foldback limiter release rate (db/samples) Field Descriptions
      192. 8.5.192 TF_CFG10 (page=0x04 address=0x5E) [reset=B7h]
        1. Table 302. Thermal foldback limiter release rate (db/samples) Field Descriptions
      193. 8.5.193 TF_CFG11 (page=0x04 address=0x5F) [reset=B0h]
        1. Table 303. Thermal foldback limiter release rate (db/samples) Field Descriptions
      194. 8.5.194 TF_CFG12 (page=0x04 address=0x60) [reset=39h]
        1. Table 304. Thermal foldback limiter temperature threshold Field Descriptions
      195. 8.5.195 TF_CFG13 (page=0x04 address=0x61) [reset=82h]
        1. Table 305. Thermal foldback limiter temperature threshold Field Descriptions
      196. 8.5.196 TF_CFG14 (page=0x04 address=0x62) [reset=60h]
        1. Table 306. Thermal foldback limiter temperature threshold Field Descriptions
      197. 8.5.197 TF_CFG16 (page=0x04 address=0x63) [reset=7Fh]
        1. Table 307. Thermal foldback limiter temperature threshold Field Descriptions
      198. 8.5.198 TF_CFG17 (page=0x04 address=0x64) [reset=2Dh]
        1. Table 308. Thermal foldback max gain reduction (dB) Field Descriptions
      199. 8.5.199 TF_CFG18 (page=0x04 address=0x65) [reset=6Ah]
        1. Table 309. Thermal foldback max gain reduction (dB) Field Descriptions
      200. 8.5.200 TF_CFG19 (page=0x04 address=0x66) [reset=86h]
        1. Table 310. Thermal foldback max gain reduction (dB) Field Descriptions
      201. 8.5.201 TF_CFG20 (page=0x04 address=0x67) [reset=6Fh]
        1. Table 311. Thermal foldback max gain reduction (dB) Field Descriptions
      202. 8.5.202 DVC_SR1 (page=0x04 address=0x6C) [reset=2h]
        1. Table 312. Volume Control slew rate for 16kHz fs Field Descriptions
      203. 8.5.203 DVC_SR2 (page=0x04 address=0x6D) [reset=79h]
        1. Table 313. Volume Control slew rate for 16kHz fs Field Descriptions
      204. 8.5.204 DVC_SR3 (page=0x04 address=0x6E) [reset=CAh]
        1. Table 314. Volume Control slew rate for 16kHz fs Field Descriptions
      205. 8.5.205 DVC_SR4 (page=0x04 address=0x6F) [reset=5Eh]
        1. Table 315. Volume Control slew rate for 16kHz fs Field Descriptions
      206. 8.5.206 CD_CFG1 (page=0x04 address=0x70) [reset=56h]
        1. Table 316. Class D gain Field Descriptions
      207. 8.5.207 CD_CFG2 (page=0x04 address=0x71) [reset=B7h]
        1. Table 317. Class D gain Field Descriptions
      208. 8.5.208 CD_CFG3 (page=0x04 address=0x72) [reset=96h]
        1. Table 318. Class D gain Field Descriptions
      209. 8.5.209 CD_CFG4 (page=0x04 address=0x73) [reset=FFh]
        1. Table 319. Class D gain Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Mono/Stereo Configuration
        2. 9.2.2.2 Boost Converter Passive Devices
        3. 9.2.2.3 EMI Passive Devices
        4. 9.2.2.4 Miscellaneous Passive Devices
  10. 10Power Supply Recommendations
    1. 10.1 Power Supplies
    2. 10.2 Power Supply Sequencing
      1. 10.2.1 Boost Supply Details
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
        1. 14.1.2 Tape and Reel Information
      2. 13.1.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.1 TDM Port

The TAS2564 provides a flexible TDM serial audio port. The port can be configured to support a variety of formats including stereo I2S, Left Justified and TDM. Mono audio playback is available via the SDIN pin. The SDOUT pin is used to transmit sample streams including speaker voltage and current sense, VBAT voltage, die temperature and channel gain.

The TDM serial audio port supports up to 16 32-bit time slots at 44.1/48 kHz, 8 32-bit time slots at a 88.2/96 kHz sample rate and 4 32-bit time slots at a 176.4/192 kHz sample rate. The device supports 2 time slots at 32 bits in width and 4 or 8 time slots at 16, 24 or 32 bits in width. Valid SBCLK to FSYNC ratios are 64, 96, 128, 192, 256, 384 and 512. The device will automatically detect the number of time slots and this does not need to be programmed.

By default, the TAS2564 will automatically detect the PCM playback sample rate. This can be disabled by setting the AUTO_RATE register bit high and manually configuring the device.

The SAMP_RATE register bits set the PCM audio sample rate when AUTO_RATE is enabled. The TAS2564 employs a robust clock fault detection engine that will automatically volume ramp down the playback path if FSYNC does not match the configured sample rate (AUTO_RATE enabled) or the ratio of SBCLK to FSYNC is not supported (minimizing any audible artifacts). Once the clocks are detected to be valid in both frequency and ratio, the device will automatically volume ramp the playback path back to the configured volume and resume playback.

When using the auto rate detection the sampling rate and SBCLK to FSYNC ration detected on the TDM bus is reported back on the read-only register FS_RATE and FS_RATIO respectively.

While the sampling rate of 192 kHz is supported, it is internally down-sampled to 96 kHz. Therefore audio content greater than 40 kHz should not be applied to prevent aliasing. This additionally effects all processing blocks like BOP and limiter which should use 96 kHz fs when accepting 192 kHz audio. It is recommend to use PurePath™ Console 3 Software to configure the device.

Table 15. PCM Auto Sample Rate Detection

AUTO_RATE SETTING
0 Enabled (default)
1 Disabled

Table 16. PCM Audio Sample Rates

SAMP_RATE[2:0] FS_RATE(read only) SAMPLE RATE
000 000
001 001 14.7kHz / 16kHz
010 010 22.05 kHz / 24 kHz
011 011 29.4 kHz / 32 kHz
100 100 44.1 kHz / 48 kHz (default)
101 101 88.2 kHz / 96 kHz
110 110 176.4 kHz / 192 kHz
111 111 Reserved

Table 17. PCM SBCLK to FSYNC Ratio Rates

FS_RATIO[3:0] SAMPLE RATE
0x0-0x3 Reserved
0x4 64
0x5 96
0x6 128
0x7 192
0x8 256
0x9 384
0xA 512
0xB-0xE Reserved
0xF Error Condition

Figure 34 and Figure 35 below illustrates the receiver frame parameters required to configure the port for playback. A frame begins with the transition of FSYNC from either high to low or low to high (set by the FRAME_START register bit). FSYNC and SDIN are sampled by SBCLK using either the rising or falling edge (set by the RX_EDGE register bit). The RX_OFFSET register bits define the number of SBCLK cycles from the transition of FSYNC until the beginning of time slot 0. This is typically set to a value of 0 for Left Justified format and 1 for an I2S format.

TAS2564 tas5770l_tdm_rx1.gifFigure 34. TDM RX Time Slot with Left Justification
TAS2564 tas5770l_tdm_rx2.gifFigure 35. TDM RX Time Slots

Table 18. TDM Start of Frame Polarity

FRAME_START POLARITY
0 Low to High on FSYNC(1)
1 High to Low on FSYNC (default)(2)
(1) When Low to High is used RX_EDGE and TX_EDGE cannot both simultaneously be set to rising edge.
(2) When High to Low is used RX_EDGE and TX_EDGE cannot both simultaneously be set to falling edge.

Table 19. TDM RX Capture Polarity

RX_EDGE FSYNC AND SDIN CAPTURE EDGE
0 Rising edge of SBCLK (default)
1 Falling edge of SBCLK

Table 20. TDM RX Start of Frame to Time Slot 0 Offset

RX_OFFSET[4:0] SBCLK CYCLES
0x00 0
0x01 1 (default)
0x02 2
... ...
0x1E 30
0x1F 31

The RX_SLEN[1:0] register bits set the length of the RX time slot. The length of the audio sample word within the time slot is configured by the RX_WLEN[1:0] register bits. The RX port will left justify the audio sample within the time slot by default, but this can be changed to right justification via the RX_JUSTIFY register bit. The TAS2564 supports mono and stereo down mix playback ([L+R]/2) via the left time slot, right time slot and time slot configuration register bits (RX_SLOT_L[3:0], RX_SLOT_R[3:0] and RX_SCFG[1:0] respectively). By default the device will playback mono from the time slot equal to the I2C base address offset for playback. The RX_SCFG[1:0] register bits can be used to override the playback source to the left time slot, right time slot or stereo down mix set by the RX_SLOT_L[3:0] and RX_SLOT_R[3:0] register bits.

If time slot selections places reception either partially or fully beyond the frame boundary, the receiver will return a null sample equivalent to a digitally muted sample.

Table 21. TDM RX Time Slot Length

RX_SLEN[1:0] TIME SLOT LENGTH
00 16-bits
01 24-bits
10 32-bits (default)
11 reserved

Table 22. TDM RX Sample Word Length

RX_WLEN[1:0] LENGTH
00 16-bits
01 20-bits
10 24-bits (default)
11 32-bits

Table 23. TDM RX Sample Justification

RX_JUSTIFY JUSTIFICATION
0 Left (default)
1 Right

Table 24. TDM RX Time Slot Select Configuration

RX_SCFG[1:0] CONFIG ORIGIN
00 Mono with Time Slot equal to I2C Address Offset (default)
01 Mono Left Channel
10 Mono Right Channel
10 Stereo Down Mix [L+R]/2

Table 25. TDM RX Left Channel Time Slot

RX_SLOT_L[3:0] TIME SLOT
0x0 0 (default)
0x1 1
... ...
0xE 14
0xF 15

Table 26. TDM RX Right Channel Time Slot

RX_SLOT_R[3:0] TIME SLOT
0x0 0
0x1 1 (default)
... ...
0xE 14
0xF 15

The TDM port can transmit a number sample streams on the SDOUT pin includingboth speaker voltage sense, speaker current sense, VBAT voltage, die temperature and channel gain. Figure 36 below illustrates the alignment of time slots to the beginning of a frame and how a given sample stream is mapped to time slots. Either the rising or falling edge of SBCLK can be used to transmit data on the SDOUT pin, which can be configured by setting the TX_EDGE register bit. The TX_OFFSET register defines the number SBCLK cycles between the start of a frame and the beginning of time slot 0. This would typically be programmed to 0 for Left Justified format and 1 for I2S format. The TDM TX can either transmit logic 0 or Hi-Z depending on the setting of the TX_FILL register bit setting. An optional bus keeper will weakly hold the state of SDOUT when all devices driving are Hi-Z. Since only one bus keeper is required on SDOUT, this feature can be disabled via the TX_KEEPEN register bit. The bus-keeper can additionally be configured to be enabled for only 1LSB cycle or always using TX_KEEPLN and to drive the full or half cycle of the LSB using TX_KEEPCY.

Each sample stream is composed of either one or two 8-bit time slots.Speaker voltage sense and speaker current sense sample streams are 16-bit precision, so they will always utilize two TX time slots. The VBAT voltage stream is 10-bit precision, and can either be transmitted left justified in a 16-bit word (using two time slots) or can be truncated to 8-bits (the top 8 MSBs) and be transmitted in a single time slot. This is configured by setting VBAT_SLEN register bit. The Die temperature and gain are both 8-bit precision and are transmitted in a single time slot.

TAS2564 tas5770l_tdm_tx.gifFigure 36. TDM Port TX Diagram

Table 27. TDM TX Transmit Polarity

TX_EDGE SDOUT TRANSMIT EDGE
0 Rising edge of SBCLK
1 Falling edge of SBCLK (default)

Table 28. TDM TX Start of Frame to Time Slot 0 Offset

TX_OFFSET[2:0] SBCLK CYCLES
0x0 0
0x1 1 (default)
0x2 2
... ...
0x6 6
0x7 7

Table 29. TDM TX Unused Bit Field Fill

TX_FILL SDOUT UNUSED BIT FIELDS
0 Transmit 0
1 Transmit Hi-Z (default)

Table 30. TDM TX SDOUT Bus Keeper Enable

TX_KEEPEN SDOUT BUS KEEPER
0 Disable bus keeper
1 Enable bus keeper (default)

Table 31. TDM TX SDOUT Bus Keeper Length

TX_KEEPLN SDOUT BUS KEEPER ENABLED FOR
0 1 LSB cycle (default)
1 Always

Table 32. TDM TX SDOUT Bus Keeper LSB Cycle

TX_KEEPCY SDOUT BUS KEEPER DRIVEN
0 full-cycle (default)
1 half-cycle

The time slot register for each sample stream defines where the MSB transmission begins. For instance, if VSNS_SLOT is set to 2, the upper 8 MSBs will be transmitted in time slot 2 and the lower 8 LSBs will be transmitted in time slot 3. Each sample stream can be individually enabled or disabled. This is useful to manage limited TDM bandwidth since it may not be necessary to transmit all streams for all devices on the bus.

It is important to ensure that time slot assignments for actively transmitted sample streams do not conflict. For instance, if VSNS_SLOT is set to 2 and ISNS_SLOT is set to 3, the lower 8 LSBs of voltage sense will conflict with the upper 8 MSBs of current sense. This will produce unpredictable transmission results in the conflicting bit slots (for example the priority is not defined).

The current and voltage values are transmitted at the full 16-bit measured values by default. The IVMON_LEN register can be used to transmit only the 8 MSB bits in one slot or 12 MSB bits values across multiple slots. The special 12-bit mode is used when only 24-bit I2S/TDM data can be processed by the host processor. The device should be configured with the voltage-sense slot and current-sense slot off by 1 slot and will consume 3 consecutive 8-bit slots. In this mode the device will transmit the first 12 MSB bits followed by the second 12 MSB bits specified by the preceding slot.

If time slot selections place transmission beyond the frame boundary, the transmitter will truncate transmission at the frame boundary.

It is recommended to keep the following slot ordering:             

ISNS_SLOT<VSNS_SLOT<VBAT_SLOT<TEMP_SLOT<GAIN_SLOT<BIL_ILIM_SLOT.

Table 33. TDM Voltage/Current Length

IVMON_LEN[1:0] LENGTH BITS
00 16 bits (default)
01 12 bits
10 8 bits
11 Reserved

Table 34. TDM Voltage Sense Time Slot

VSNS_SLOT[5:0] SLOT
0x00 0
0x01 1
0x02 2 (default)
... ...
0x3E 62
0x3F 63

Table 35. TDM Voltage Sense Transmit Enable

VSNS_TX STATE
0 Disabled (default)
1 Enabled

Table 36. TDM Current Sense Time Slot

ISNS_SLOT[5:0] SLOT
0x00 0 (default)
0x01 1
0x02 2
... ...
0x3E 62
0x3F 63

Table 37. TDM Current Sense Transmit Enable

ISNS_TX STATE
0 Disabled (default)
1 Enabled

Table 38. TDM VBAT Time Slot

VBAT_SLOT[5:0] SLOT
0x00 0
0x01 1
... ...
0x04 4 (default)
... ...
0x3E 62
0x3F 63

Table 39. TDM VBAT Time Slot Length

VBAT_SLEN SLOT LENGTH
0 Truncate to 8-bits (default)
1 Left justify to 16-bits

Table 40. TDM VBAT Transmit Enable

VBAT_TX STATE
0 Disabled (default)
1 Enabled

Table 41. TDM Temp Sensor Time Slot

TEMP_SLOT[5:0] SLOT
0x00 0
0x01 1
... ...
0x05 5 (default)
... ...
0x3E 62
0x3F 63

Table 42. TDM Temp Sensor Transmit Enable

TEMP_TX STATE
0 Disabled (default)
1 Enabled

The following sample streams are part of the Inter Chip Limiter Alignment system. These data streams can be routed over the audio TDM bus.

Table 43. TDM Limiter Gain Reduction Time Slot

GAIN_SLOT[5:0] SLOT
0x00 0
0x01 1
... ...
0x06 6 (default)
... ...
0x3E 62
0x3F 63

Table 44. TDM Limiter Gain Reduction Transmit Enable

GAIN_TX STATE
0 Disabled (default)
1 Enabled

Table 45. TDM Boost Sync Time Slot

BST_SLOT[5:0] SLOT
0x00 0
0x01 1
... ...
0x07 7 (default)
... ...
0x3E 62
0x3F 63

Table 46. TDM Boost Sync Enable

BST_TX STATE
0 Disabled (default)
1 Enabled