SLOS795F September   2013  – October 2017 TAS5414C-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements for I2C Interface Signals
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descption
      1. 7.3.1  Preamplifier
      2. 7.3.2  Pulse-Width Modulator (PWM)
      3. 7.3.3  Gate Drive
      4. 7.3.4  Power FETs
      5. 7.3.5  Load Diagnostics
      6. 7.3.6  Protection and Monitoring
      7. 7.3.7  I2C Serial Communication Bus
      8. 7.3.8  I2C Bus Protocol
      9. 7.3.9  Hardware Control Pins
      10. 7.3.10 AM Radio Avoidance
    4. 7.4 Device Functional Modes
      1. 7.4.1 Audio Shutdown and Restart Sequence
      2. 7.4.2 Latched-Fault Shutdown and Restart Sequence Control
    5. 7.5 Programming
      1. 7.5.1 Random Write
      2. 7.5.2 Sequential Write
      3. 7.5.3 Random Read
      4. 7.5.4 Sequential Read
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Hardware and Software Design
        2. 8.2.2.2 Parallel Operation (PBTL)
        3. 8.2.2.3 Input Filter Design
        4. 8.2.2.4 Amplifier Output Filtering
        5. 8.2.2.5 Line Driver Applications
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Consideration
    4. 10.4 Electrical Connection of Heat Slug and Heat Sink
    5. 10.5 EMI Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Links
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PHD|64
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

The pin assignments are shown as follows.

DKE Package
(Top View)
TAS5414C-Q1 TAS5424C-Q1 pinout_dkd44_5424_los673_r1.gif
PHD Package
(Top View)
TAS5414C-Q1 TAS5424C-Q1 pinout_phd64_5414_los673_r1.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME DKE PACKAGE PHD PACKAGE
TAS5424C-Q1
NO.		 TAS5414C-Q1
NO.
A_BYP 14 11 PBY Bypass pin for the AVDD analog regulator
CLIP_OTW 10 6 DO Reports CLIP, OTW, or both. It also reports tweeter detection during tweeter mode. Open-drain
CP 34 41 CP Top of main storage capacitor for charge pump (bottom goes to PVDD)
CPC_BOT 33 40 CP Bottom of flying capacitor for charge pump
CPC_TOP 35 42 CP Top of flying capacitor for charge pump
D_BYP 9 5 PBY Bypass pin for DVDD regulator output
FAULT 5 1 DO Global fault output (open drain): UV, OV, OTSD, OCSD, DC
GND 7, 11, 12, 28, 29, 32, 38, 39 3, 7, 8, 9, 12, 14, 16, 17, 21, 22, 23, 24, 25, 26, 30, 31, 32, 35, 38, 39, 43, 46, 49, 50, 51, 55, 56, 57, 58, 59, 60 GND Ground
I2C_ADDR 2 62 AI I2C address bit
IN1_M 16 N/A AI Inverting analog input for channel 1 (TAS5424C-Q1 only)
IN1_P 15 13 AI Non-inverting analog input for channel 1
IN2_M 18 N/A AI Inverting analog input for channel 2 (TAS5424C-Q1 only)
IN2_P 17 15 AI Non-inverting analog input for channel 2
IN3_M 20 N/A AI Inverting analog input for channel 3 (TAS5424C-Q1 only)
IN3_P 19 19 AI Non-inverting analog input for channel 3
IN4_M 22 N/A AI Inverting analog input for channel 4 (TAS5424C-Q1 only)
IN4_P 21 20 AI Non-inverting analog input for channel 4
IN_M N/A 18 ARTN Signal return for the four analog channel inputs (TAS5414C-Q1 only)
MUTE 6 2 AI Gain ramp control: mute (low), play (high)
OSC_SYNC 1 61 DI/DO Oscillator input from master or output to slave amplifiers
OUT1_M 41 48 PO – polarity output for bridge 1
OUT1_P 40 47 PO + polarity output for bridge 1
OUT2_M 37 45 PO – polarity output for bridge 2
OUT2_P 36 44 PO + polarity output for bridge 2
OUT3_M 31 37 PO – polarity output for bridge 3
OUT3_P 30 36 PO + polarity output for bridge 3
OUT4_M 27 34 PO – polarity output for bridge 4
OUT4_P 26 33 PO + polarity output for bridge 4
PVDD 23, 24, 25, 42, 43, 44 27, 28, 29, 52, 53, 54 PWR PVDD supply
REXT 13 10 AI Precision resistor pin to set analog reference
SCL 4 64 DI I2C clock input from system I2C master
SDA 3 63 DI/DO I2C data I/O for communication with system I2C master
STANDBY 8 4 DI Active-low STANDBY pin. Standby (low), power up (high)
(1) DI = digital input, DO = digital output, AI = analog input, ARTN = analog signal return, PWR = power supply, PBY = power bypass, PO = power output, GND = ground, CP = charge pump.