JAJSCS5 December   2016 TAS5414C

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements for I2C Interface Signals
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descption
      1. 7.3.1  Preamplifier
      2. 7.3.2  Pulse-Width Modulator (PWM)
      3. 7.3.3  Gate Drive
      4. 7.3.4  Power FETs
      5. 7.3.5  Load Diagnostics
      6. 7.3.6  Protection and Monitoring
      7. 7.3.7  I2C Serial Communication Bus
      8. 7.3.8  I2C Bus Protocol
      9. 7.3.9  Hardware Control Pins
      10. 7.3.10 AM Radio Avoidance
    4. 7.4 Device Functional Modes
      1. 7.4.1 Audio Shutdown and Restart Sequence
      2. 7.4.2 Latched-Fault Shutdown and Restart Sequence Control
    5. 7.5 Programming
      1. 7.5.1 Random Write
      2. 7.5.2 Sequential Write
      3. 7.5.3 Random Read
      4. 7.5.4 Sequential Read
    6. 7.6 Register Maps
      1. 7.6.1  Register Summary
      2. 7.6.2  Registers
        1. 7.6.2.1 Fault Register 1 (0x00) Protection
      3. 7.6.3  Fault Register 2 (0x01) Protection
      4. 7.6.4  Diagnostic Register 1 (0x02) Load Diagnostics
      5. 7.6.5  Diagnostic Register 2 (0x03) Load Diagnostics
      6. 7.6.6  External Status Register 1 (0x04) Fault Detection
      7. 7.6.7  External Status Register 2 (0x05) Output State of Individual Channels
      8. 7.6.8  External Status Register 3 (0x06) Play and Mute Modes
      9. 7.6.9  External Status Register 4 (0x07) Load Diagnostics
      10. 7.6.10 External Control Register 1 (0x08) Gain Select
      11. 7.6.11 External Control Register 2 (0x09) Overcurrent Control
      12. 7.6.12 External Control Register 3 (0x0A) Switching Frequency Select and Clip_OTW Configuration
      13. 7.6.13 External Control Register 4 (0x0B) Load Diagnostics and Master/Slave Control
      14. 7.6.14 External Control Register 5 (0x0C) Output Control
      15. 7.6.15 External Control Register 6 (0x0D) Output Control
      16. 7.6.16 External Control Register 7 (0x10) Miscellaneous Selection
      17. 7.6.17 External Status Register 5 (0x13) Overtemperature and Thermal Foldback Status
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Hardware and Software Design
        2. 8.2.2.2 Parallel Operation (PBTL)
        3. 8.2.2.3 Input Filter Design
        4. 8.2.2.4 Amplifier Output Filtering
        5. 8.2.2.5 Line Driver Applications
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Consideration
    4. 10.4 Electrical Connection of Heat Slug and Heat Sink
    5. 10.5 EMI Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
      2. 11.1.2 デバイスの項目表記
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
PVDD DC supply voltage range Relative to GND –0.3 30 V
PVDDMAX Pulsed supply voltage range t ≤ 100 ms exposure –1 50 V
PVDDRAMP Supply voltage ramp rate 15 V/ms
IPVDD Externally imposed dc supply current per PVDD or GND pin ±12 A
IPVDD_MAX Pulsed supply current per PVDD pin (one shot) t < 100 ms 17 A
IO Maximum allowed dc current per output pin ±13.5 A
IO_MAX (1) Pulsed output current per output pin (single pulse) t < 100 ms ±17 A
IIN_MAX Maximum current, all digital and analog input pins(2) DC or pulsed ±1 mA
IMUTE_MAX Maximum current on MUTE pin DC or pulsed ±20 mA
IIN_ODMAX Maximum sink current for open-drain pins 7 mA
VLOGIC Input voltage range for pin relative to GND (SCL, SDA, I2C_ADDR pins) Supply voltage range:
6V < PVDD < 24 V		 –0.3 6 V
VMUTE Voltage range for MUTE pin relative to GND Supply voltage range:
6 V < PVDD < 24 V		 –0.3 7.5 V
VSTANDBY Input voltage range for STANDBY pin Supply voltage range:
6 V < PVDD < 24 V		 –0.3 5.5 V
VOSC_SYNC Input voltage range for OSC_SYNC pin relative to GND Supply voltage range:
6 V < PVDD < 24 V		 –0.3 3.6 V
VGND Maximum voltage between GND pins ±0.3 V
VAIN_AC_MAX Maximum ac-coupled input voltage for TAS5414C(2), analog input pins Supply voltage range:
6 V < PVDD < 24 V		 1.9 Vrms
TJ Maximum operating junction temperature range –55 150 °C
Tstg Storage temperature –55 150 °C
(1) Pulsed current ratings are maximum survivable currents externally applied to the device. The device may encounter high currents during reverse-battery, fortuitous open-ground, and fortuitous open-supply fault conditions.
(2) See the Application Information section for information on analog input voltage and ac coupling.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2500 V
Charged device model (CDM),
per AEC Q100-011
PHD Package 		Corner pins excluding SCL ±750 V
All pins (including SCL) except CP and CP_Top ±600
CP and CP_Top pins ±400
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions(1)

MIN TYP MAX UNIT
PVDDOP DC supply voltage range relative to GND 6 14.4 24 V
VAIN (2) Analog audio input signal level AC-coupled input voltage 0 0.25–1(3) Vrms
TA Ambient temperature –20 105 °C
TJ Junction temperature An adequate heat sink is required to keep TJ within specified range. –40 115 °C
RL Nominal speaker load impedance 2 4 Ω
VPU Pullup voltage supply (for open-drain logic outputs) 3 3.3 or 5 5.5 V
RPU_EXT External pullup resistor on open-drain logic outputs Resistor connected between open-drain logic output and VPU supply 10 50 kΩ
RPU_I2C I2C pullup resistance on SDA and SCL pins 1 4.7 10 kΩ
RI2C_ADD Total resistance of voltage divider for I2C address slave 1 or slave 2, connected between D_BYP and GND pins 10 50 kΩ
RREXT External resistance on REXT pin 1% tolerance required 19.8 20 20.2 kΩ
CD_BYP ,
CA_BYP 		External capacitance on D_BYP and A_BYP pins 10 120 nF
COUT External capacitance to GND on OUT_X pins 150 680 nF
CIN External capacitance to analog input pin in series with input signal 0.47 μF
CFLY Flying capacitor on charge pump 0.47 1 1.5 μF
CP Charge pump capacitor 50V needed for Load Dump 0.47 1 1.5 μF
CMUTE MUTE pin capacitor 100 220 1000 nF
COSCSYNC_MAX Allowed loading capacitance on OSC_SYNC pin 75 pF
(1) The Recommended Operating Conditions table specifies only that the device is functional in the given range. See the Electrical Characteristics table for specified performance limits.
(2) Signal input for full unclipped output with gains of 32 dB, 26 dB, 20 dB, and 12 dB
(3) Maximum recommended input voltage is determined by the gain setting.

6.4 Thermal Information

PARAMETER VALUE (Typical) UNIT
RθJC Junction-to-case (heat slug) thermal resistance, PHD package 1.2 °C/W
RθJA Junction-to-ambient thermal resistance This device is not intended to be used without a heatsink. Therefore, RθJA is not specified. Refer to the Thermal Information section. °C/W

6.5 Electrical Characteristics

Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Pout = 1 W/ch, Rext = 20 kΩ, AES17 filter, default I2C settings, master-mode operation (see Figure 36)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING CURRENT
IPVDD_IDLE PVDD idle current All four channels in MUTE mode 170 220 mA
IPVDD_Hi-Z All four channels in Hi-Z mode 93 mA
IPVDD_STBY PVDD standby current STANDBY mode, TJ ≤ 85°C 2 10 μA
OUTPUT POWER
POUT Output power per channel 4 Ω, PVDD = 14.4 V, THD+N ≤ 1%, 1 kHz, Tc = 75°C 23 W
4 Ω, PVDD = 14.4 V, THD+N = 10%, 1 kHz, Tc = 75°C 25 28
4 Ω, PVDD = 24 V, THD+N = 10%, 1 kHz, Tc = 75°C 63 79
2 Ω, PVDD = 14.4 V, THD+N = 1%, 1 kHz, Tc = 75°C 38
2 Ω, PVDD = 14.4 V, THD+N = 10%, 1 kHz, Tc = 75°C 40 50
PBTL 2-Ω operation, PVDD = 24 V, THD+N = 10%, 1 kHz, Tc = 75°C 150
PBTL 1-Ω operation, PVDD = 14.4 V, THD+N = 10%, 1 kHz, Tc = 75°C 90
EFFP Power efficiency 4 channels operating, 23-W output power/ch, L = 10 μH, TJ ≤ 85°C 90%
AUDIO PERFORMANCE
VNOISE Noise voltage at output Zero input, and A-weighting 60 100 μV
Channel crosstalk P = 1 W, f = 1 kHz, enhanced crosstalk enabled via I2C (reg. 0x10) 70 85 dB
PSRR Power-supply rejection ratio PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz 60 75 dB
THD+N Total harmonic distortion + noise P = 1 W, f = 1 kHz 0.02% 0.1%
fS Switching frequency Switching frequency selectable for AM interference avoidance 336 357 378 kHz
392 417 442
470 500 530
RAIN Analog input resistance Internal shunt resistance on each input pin 63 85 106 kΩ
VIN_CM Common-mode input voltage AC-coupled common-mode input voltage (zero differential input) 1.3 Vrms
VCM_INT Internal common-mode input bias voltage Internal bias applied to IN_M pin 3.3 V
G Voltage gain (VO/VIN) Source impedance = 0 Ω, gain measurement taken at 1 W of power per channel 11 12 13 dB
19 20 21
25 26 27
31 32 33
GCH Channel-to-channel variation Any gain commanded –1 0 1 dB
PWM OUTPUT STAGE
RDS(on) FET drain-to-source resistance Not including bond wire resistance, TJ = 25°C 65 90 mΩ
VO_OFFSET Output offset voltage Zero input signal, G = 26 dB ±10 ±50 mV
PVDD OVERVOLTAGE (OV) PROTECTION
VOV_SET PVDD overvoltage shutdown set 24.6 26.4 28.2 V
VOV_CLEAR PVDD overvoltage shutdown clear 24.4 25.9 27.4 V
PVDD UNDERVOLTAGE (UV) PROTECTION
VUV_SET PVDD undervoltage shutdown set 4.9 5.3 5.6 V
VUV_CLEAR PVDD undervoltage shutdown clear 6.2 6.6 7 V
AVDD
VA_BYP A_BYP pin voltage 6.5 V
VA_BYP_UV_SET A_BYP UV voltage 4.8 V
VA_BYP_UV_CLEAR Recovery voltage A_BYP UV 5.3 V
DVDD
VD_BYP D_BYP pin voltage 3.3 V
POWER-ON RESET (POR)
VPOR PVDD voltage for POR I2C active above this voltage 4 V
VPOR_HY PVDD recovery hysteresis voltage for POR 0.1 V
REXT
VREXT Rext pin voltage 1.27 V
CHARGE PUMP (CP)
VCPUV_SET CP undervoltage 4.8 V
VCPUV_CLEAR Recovery voltage for CP UV 4.9 V
OVERTEMPERATURE (OT) PROTECTION
TOTW1_CLEAR Junction temperature for overtemperature warning 96 112 128 °C
TOTW1_SET /
TOTW2_CLEAR 		106 122 138 °C
TOTW2_SET /
TOTW3_CLEAR 		116 132 148 °C
TOTW3_SET /
TOTSD_CLEAR 		126 142 158 °C
TOTSD Junction temperature for overtemperature shutdown 136 152 168 °C
TFB Junction temperature for overtemperature foldback Per channel 130 150 170 °C
CURRENT LIMITING PROTECTION
ILIM Current limit (load current) Level 1 5.5 7.3 9 A
Level 2 (default) 10.6 12.7 15
OVERCURRENT (OC) SHUTDOWN PROTECTION
IMAX Maximum current (peak output current) Level 1 7.8 9.8 12.2 A
Level 2 (default), Any short to supply, ground, or other channels 11.9 14.8 17.7
TWEETER DETECT
ITH_TW Load-current threshold for tweeter detect 330 445 560 mA
ILIM_TW Load-current limit for tweeter detect 2.1 A
STANDBY MODE
VIH STANDBY input voltage for logic-level high   2 V
VIL STANDBY input voltage for logic-level low   0.7 V
ISTBY STANDBY pin current 0.1 0.2 μA
MUTE MODE
GMUTE Output attenuation MUTE pin ≤ 0.5 V for 200ms or I2C Mute Enabled 100 dB
DC DETECT
VTH_DC_TOL DC detect threshold tolerance 25%
tDCD DC detect step-response time for four channels 5.3 s
CLIP_OTW REPORT
VOH_CLIPOTW CLIP_OTW pin output voltage for logic level high (open-drain logic output) External 47-kΩ pullup resistor to 3 V–5.5 V 2.4 V
VOL_CLIPOTW CLIP_OTW pin output voltage for logic level low (open-drain logic output) 0.5 V
tDELAY_CLIPDET CLIP_OTW signal delay when output clipping detected 20 μs
FAULT REPORT
VOH_FAULT FAULT pin output voltage for logic-level high (open-drain logic output) External 47-kΩ pullup resistor to 3 V–5.5 V 2.4 V
VOL_FAULT FAULT pin output voltage for logic-level low (open-drain logic output) 0.5
OPEN, SHORT DIAGNOSTICS
RS2P, RS2G Maximum resistance to detect a short from OUT pin(s) to PVDD or ground 200 Ω
ROPEN_LOAD Minimum load resistance to detect open circuit Including speaker wires 300 740 1300 Ω
RSHORTED_LOAD Maximum load resistance to detect short circuit Including speaker wires 0.5 1 1.5 Ω
I2C ADDRESS DECODER
tLATCH_I2CADDR Time delay to latch I2C address after POR 300 μs
VI2C_ADDR Voltage on I2C_ADDR pin for address 0 Connect to GND 0% 0% 15% VD_BYP
Voltage on I2C_ADDR pin for address 1 External resistors in series between D_BYP and GND as a voltage divider 25% 35% 45%
Voltage on I2C_ADDR pin for address 2 55% 65% 75%
Voltage on I2C_ADDR pin for address 3 Connect to D_BYP 85% 100% 100%
I2C
tHOLD_I2C Power-on hold time before I2C communication STANDBY high 1 ms
fSCL SCL clock frequency 400 kHz
VIH SCL pin input voltage for logic-level high RPU_I2C = 5-kΩ pullup, supply voltage = 3.3 V or 5 V 2.1 5.5 V
VIL SCL pin input voltage for logic-level low –0.5 1.1 V
VOH SDA pin output voltage for logic-level high I2C read, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V		 2.4 V
VO SDA pin output voltage for logic-level low I2C read, 3-mA sink current 0.4 V
VIH SDA pin input voltage for logic-level high I2C write, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V		 2.1 5.5 V
VIL SDA pin input voltage for logic-level low I2C write, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V		 –0.5 1.1 V
C I Capacitance for SCL and SDA pins 10 pF
OSCILLATOR
VOH OSC_SYNC pin output voltage for logic-level high I2C_ADDR pin set to MASTER mode 2.4 V
VOL OSC_SYNC pin output voltage for logic-level low 0.5 V
VIH OSC_SYNC pin input voltage for logic-level high I2C_ADDR pin set to SLAVE mode 2 V
VIL OSC_SYNC pin input voltage for logic-level low 0.8 V
fOSC_SYNC OSC_SYNC pin clock frequency I2C_ADDR pin set to MASTER mode, fS = 500 kHz 3.76 4 4.24 MHz
I2C_ADDR pin set to MASTER mode, fS = 417 kHz 3.13 3.33 3.63
I2C_ADDR pin set to MASTER mode, fS = 357 kHz 2.68 2.85 3.0

6.6 Timing Requirements for I2C Interface Signals

over recommended operating conditions (unless otherwise noted)
MIN TYP MAX UNIT
tr Rise time for both SDA and SCL signals 300 ns
tf Fall time for both SDA and SCL signals 300 ns
tw(H) SCL pulse duration, high 0.6 μs
tw(L) SCL pulse duration, low 1.3 μs.
tsu2 Setup time for START condition 0.6 μs
th2 START condition hold time until generation of first clock pulse 0.6 μs
tsu1 Data setup time 100 ns
th1 Data hold time 0(1) ns
tsu3 Setup time for STOP condition 0.6 μs
CB Load capacitance for each bus line 400 pF
(1) A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL.
TAS5414C T0027-01.gif Figure 1. SCL and SDA Timing
TAS5414C T0028-01.gif Figure 2. Timing for Start and Stop Conditions

6.7 Typical Characteristics

TAS5414C THDVsOutputPower.png Figure 3. THD+N vs BTL Output Power at 1kHz
TAS5414C THDvsFreq.png Figure 5. THD+N vs Frequency at 1 Watt
TAS5414C OutputNoise.png Figure 7. Noise FFT
TAS5414C G008_LOS514.gif Figure 9. Device Power Dissipation
Four Channels at 4 Ω Each
TAS5414C THDVsOutputPowerPBTL.png Figure 4. THD+N vs PBTL Output Power at 1kHz
TAS5414C Crosstalk.png Figure 6. Crosstalk vs Frequency
TAS5414C G007_LOS514.gif Figure 8. Efficiency
Four Channels AT 4 Ω Each