SLOS814D March   2014  – September 2016 TAS5421-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements for I2C Interface Signals
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Audio Input and Preamplifier
      2. 7.3.2 Pulse-Width Modulator (PWM)
      3. 7.3.3 Gate Drive
      4. 7.3.4 Power FETs
      5. 7.3.5 Load Diagnostics
      6. 7.3.6 Protection and Monitoring
      7. 7.3.7 I2C Serial Communication Bus
        1. 7.3.7.1 I2C Bus Protocol
        2. 7.3.7.2 Random Write
        3. 7.3.7.3 Random Read
        4. 7.3.7.4 Sequential Read
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hardware Control Pins
      2. 7.4.2 EMI Considerations
      3. 7.4.3 Operating Modes and Faults
    5. 7.5 Register Maps
      1. 7.5.1 I2C Address Register Definitions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Amplifier Output Filtering
        2. 8.2.1.2 Amplifier Output Snubbers
        3. 8.2.1.3 Bootstrap Capacitors
        4. 8.2.1.4 Analog Audio Input Filter
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Unused Pin Connections
          1. 8.2.2.1.1 MUTE Pin
          2. 8.2.2.1.2 STANDBY Pin
          3. 8.2.2.1.3 I2C Pins (SDA and SCL)
          4. 8.2.2.1.4 Terminating Unused Outputs
          5. 8.2.2.1.5 Using a Single-Ended Audio Input
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Top Layer
      2. 10.2.2 Second Layer - Signal Layer
      3. 10.2.3 Third Layer - Power Layer
      4. 10.2.4 Bottom Layer - Ground Layer
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resource
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Input voltage DC supply voltage range, V(PVDD) Relative to GND –0.3 30 V
Pulsed supply voltage range, V(PVDD_MAX) t ≤ 400 ms exposure –1 40
Supply voltage ramp rate, ΔV(PVDD_RAMP) 15 V/ms
For SCL, SDA, and STANDBY pins Relative to GND –0.3 5 V
For IN_N, IN_P, FAULT, and MUTE pins Relative to GND –0.3 6.5
Current DC current on PVDD, GND and OUTx pins, I(PVDD), IO ±4 A
Maximum current, on all input pins, I(IN_MAX) (2) ±1 mA
Maximum sink current for open-drain pin, I(IN_ODMAX) 7
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) See the Application and Implementation section for information on analog input voltage and ac coupling.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±3500 V
Charged-device model (CDM), per AEC Q100-011 ±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
V(PVDD_OP) Supply voltage range relative to GND. Includes ac transients, requires proper decoupling.(3) 4-Ω ±20% load (or higher)
 4.5 14.4 18 V
2-Ω ±20% load 5 14.4 18
V(PVDD_RIPPLE) Maximum ripple on PVDD V(PVDD) < 8 V 1 Vpp
V(AIN)(1) Analog audio input-signal level AC-coupled input voltage 0 0.25–1(2) Vrms
V(IH_STANDBY) MUTE and STANDBY pins input voltage for logic-level high 2 V
V(IL_STANDBY) MUTE and STANDBY pins input voltage for logic-level low 0.7 V
V(IH_SCL) SCL pin input voltage for logic-level high R(PU_I2C) = 4.7-kΩ pullup, supply voltage = 3.3 V or 5 V 2.1 5.5 V
V(IH_SDA) SDA pin input voltage for logic-level high R(PU_I2C) = 4.7-kΩ pullup, supply voltage = 3.3 V or 5 V 2.1 5.5 V
V(IL_SCL) SCL pin input voltage for logic-level low R(PU_I2C) = 4.7-kΩ pullup, supply voltage = 3.3 V or 5 V –0.5 1.1 V
V(IL_SDA) SDA pin input voltage for logic-level low R(PU_I2C) = 4.7-kΩ pullup, supply voltage = 3.3 V or 5 V –0.5 1.1 V
TA Ambient temperature –40 125 °C
R(L) Nominal speaker load impedance When using low-impedance loads, do not exceed overcurrent limit. 2 4 16 Ω
V(PU) Pullup voltage supply (for open-drain logic outputs) 3 3.3 3.6 V
R(PU_EXT) External pullup resistor on open-drain logic outputs Resistor connected between open-drain logic output and V(PU) supply. 10 50 kΩ
R(PU_I2C) I2C pullup resistance on SDA and SCL pins 1 4.7 10 kΩ
C(PVDD) External capacitor on the PVDD pin, typical value ± 20%(3) 10 μF
C(BYP) External capacitor on the BYP pin, typical value ± 10% 1 μF
C(OUT) External capacitance to GND on OUT_X pins 4 μF
C(IN) External capacitance to analog input pin in series with input signal 1 μF
C(BSTN), C(BSTP) External boostrap capacitor, typical value ± 20% 220 nF
(1) Signal input for full unclipped output with gains of 36 dB, 32 dB, 26 dB, and 20 dB
(2) Maximum recommended input voltage is determined by the gain setting.
(3) See the Power Supply Recommendations section.

6.4 Thermal Information

THERMAL METRIC(1) TAS5421-Q1 UNIT
PWP (HTSSOP)
16 PINS
RθJA Junction-to-ambient thermal resistance 39.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 24.9 °C/W
RθJB Junction-to-board thermal resistance 20 °C/W
ψJT Junction-to-top characterization parameter 0.6 °C/W
ψJB Junction-to-board characterization parameter 19.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

TC = 25°C, PVDD = 14.4 V, RL = 4 Ω, P(O) = 1 W/ch, AES17 filter, default I2C settings (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING CURRENT
PVDD idle current In PLAY mode, no audio present 16 mA
PVDD standby current STANDBY mode, MUTE = 0 V 5 20 µA
OUTPUT POWER
Output power per channel 4 Ω, THD+N ≤ 1%, 1 kHz, TC = 75°C 18 W
4 Ω, THD+N = 10%, 1 kHz, TC = 75°C 22
Power efficiency 4 Ω, P(O) = 22 W (10% THD) 85%
AUDIO PERFORMANCE
Noise voltage at output G = 20 dB, zero input, and A-weighting 65 µV
Common-mode rejection ratio f = 1 kHz, 100 mVrms referenced to GND, G = 20 dB 63 dB
Power-supply rejection ratio PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz 75
Total harmonic distortion + noise P(O) = 1 W, f = 1 kHz 0.05% dB
Switching frequency Switching frequency selectable for AM interference avoidance 400 kHz
500
Internal common-mode input bias voltage Internal bias applied to IN_N, IN_P pins 3 V
Voltage gain (VO / VIN) Source impedance = 0 Ω, P(O) = 1 W 19 20 21 dB
25 26 27
31 32 33
35 36 37
PWM OUTPUT STAGE
FET drain-to-source resistance TJ = 25°C 180 mΩ
Output offset voltage Zero input signal, G = 20 dB ±25 mV
PVDD OVERVOLTAGE (OV) PROTECTION
PVDD overvoltage-shutdown set 19.5 21 22.5 V
PVDD overvoltage-shutdown hysteresis 0.6 V
PVDD UNDERVOLTAGE (UV) PROTECTION
PVDD undervoltage-shutdown set 3.6 4 4.4 V
PVDD undervoltage-shutdown hysteresis 0.25 V
BYP
BYP pin voltage 6.4 6.9 7.4 V
POWER-ON RESET (POR)
PVDD voltage for POR 4.1 V
PVDD recovery hysteresis voltage for POR 0.3 V
OVERTEMPERATURE (OT) PROTECTION
Junction temperature for overtemperature shutdown 155 170 °C
Junction temperature overtemperature shutdown hystersis 15 °C
OVERCURRENT (OC) SHUTDOWN PROTECTION
Maximum current (peak output current) 3.5 A
STANDBY PIN
STANDBY pin current 0.1 0.2 µA
DC DETECT
DC detect threshold 2.9 V
DC detect step response time 700 ms
FAULT REPORT
FAULT pin output voltage for logic-level high (open-drain logic output) External 47-kΩ pullup resistor to 3.3 V 2.4 V
FAULT pin output voltage for logic-level low (open-drain logic output) External 47-kΩ pullup resistor to 3.3 V 0.5 V
LOAD DIAGNOSTICS
Resistance to detect a short from OUT pin(s) to PVDD or ground 200 Ω
Open-circuit detection threshold Including speaker wires 70 95 120 Ω
Short-circuit detection threshold Including speaker wires 0.9 1.2 1.5 Ω
I2C
SDA pin output voltage for logic-level high R(PU_I2C) = 4.7-kΩ pullup, supply voltage = 3.3 V or 5 V 2.4 V
SDA pin output voltage for logic-level low 3-mA sink current 0.4 V
Capacitance for SCL and SDA pins 10 pF
Capacitance for SDA pin STANDBY mode 30 pF

6.6 Timing Requirements for I2C Interface Signals

over recommended operating conditions (unless otherwise noted)
MIN NOM MAX UNIT
f(SCL) SCL clock frequency 400 kHz
tr Rise time for both SDA and SCL signals 300 ns
tf Fall time for both SDA and SCL signals 300 ns
tw(H) SCL pulse duration, high 0.6 µs
tw(L) SCL pulse duration, low 1.3 µs
tsu(2) Setup time for START condition 0.6 µs
th(2) START condition hold time before generation of first clock pulse 0.6 µs
tsu(1) Data setup time 100 ns
th(1) Data hold time 0(1) ns
tsu(3) Setup time for STOP condition 0.6 µs
C(B) Load capacitance for each bus line 400 pF
(1) A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL.
TAS5421-Q1 T0027-03_SLOS814.gif Figure 1. SCL and SDA Timing
TAS5421-Q1 T0028-02_SLOS814.gif Figure 2. Timing for Start and Stop Conditions

6.7 Typical Characteristics

PVDD = 14.4 V, TA = 25ºC, P(O) = 1 W, 1-kHz input, default I2C settings (unless otherwise noted)
TAS5421-Q1 D001_SLOS814.gif
Gain = 26 dB f(SW) = 400 kHz TA = 25ºC
V(PVDD) = 14.4 V
Figure 3. Efficiency vs Output Power
TAS5421-Q1 D003_SLOS814.gif
Figure 5. Output Power vs PVDD
TAS5421-Q1 D005_SLOS814.gif
Figure 7. Noise FFT With –60-dB Output
TAS5421-Q1 D007_SLOS814.gif
Figure 9. Overcurrent Threshold vs Temperature
TAS5421-Q1 D002_SLOS814.gif
Figure 4. THD+N vs Output Power
TAS5421-Q1 D004_SLOS814.gif
Figure 6. THD+N vs Frequency
TAS5421-Q1 D006_SLOS814.gif
Figure 8. Noise FFT With 1-W Output