7.3.1.1 Input I²S Timing

I²S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 64 f_S is used to clock in the data. From the time the LRCLK signal changes state to the first bit of data on the data lines is a delay of one bit clock. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5548 masks unused trailing data bit positions.

Figure 15. I²S 64-f_S Format

7.3.1.2 Left-Justified Timing

Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 64 f_S is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5548 masks unused trailing data bit positions.

Figure 16. Left-Justified 64-f_S Format

7.3.1.3 Right-Justified Timing

Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 64 f_S is used to clock in the data. The first bit of data appears on the data lines eight bit-clock periods (for 24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before LRCLK transitions. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5548 masks unused leading data bit positions.

Figure 17. Right-Justified 64-f_S Format

7.3.5.1 DC Blocking (High-Pass Filter Enable/Disable)

Each input channel incorporates a first-order, digital, high-pass filter to block potential dc components. The filter –3-dB point is approximately 2-Hz at the 96-kHz sampling rate. The high-pass filter can be enabled and disabled via the I²C system control register 1 (0x03 bit D7). The default setting is 1 (high-pass filter enabled).

7.3.5.2 AM Interference Avoidance

Digital amplifiers can degrade AM reception as a result of their RF emissions. Texas Instruments' patented AM interference-avoidance circuit provides a flexible system solution for a wide variety of digital audio architectures. During AM reception, the TAS5548 adjusts the radiated emissions to provide an emission-clear zone for the tuned AM frequency. The inputs to the TAS5548 for this operation are the tuned AM frequency, the IF frequency, and the sample rate. This PWM rate modification is done by modifying the output rate of the Sample Rate Converter, and the following DSP and PWM modulator.

7.3.6.1 I²C Status Registers

The TAS5548 has two status registers that provide general device information. These are the general status register 0 (0x01) and the error status register (0x02).

7.3.6.2 TAS5548 Pin Controls

The TAS5548 provide a number of terminal controls to manage the device operation. These controls are:

• RESET
• PDN
• BKND_ERR
• HP_SEL
• MUTE
• PSVC
• EMO1 (see System Power Contoller section)
• EMO2 (see System Power Contoller section)

7.3.6.2.6 Power-Supply Volume Control (PSVC)

The TAS5548 supports volume control both by conventional digital gain/attenuation and by a combination of digital and analog gain/attenuation. Varying the H-bridge power-supply voltage performs the analog volume control function. The benefits of using power-supply volume control (PSVC) are reduced idle channel noise, improved signal resolution at low volumes, increased dynamic range, and reduced radio frequency emissions at reduced power levels. The PSVC is enabled via I²C. When enabled, the PSVC provides a PWM output that is filtered to provide a reference voltage for the power supply. The power-supply adjustment range can be set for –-12.04, –18.06, or –24.08 dB, to accommodate a range of variable power-supply designs.

Figure 18 and Figure 19 show how power-supply and digital gains can be used together.

The volume biquad (0xCF) can be used to implement a low-pass filter in the digital volume control to match the PSVC volume transfer function. Note that if the PVSC function is not used, the volume biquad is all-pass (default).

Figure 18. Power-Supply and Digital Gains (Linear Space)

Figure 19. Power-Supply and Digital Gains (Log Space)

Table 5. Serial Data Formats

7.4.7.1 TAS5548 Audio-Processing Configurations

The 32-kHz to 96-kHz configuration supports eight channels of data processing that can be configured either as eight channels, or as six channels with two channels for separate stereo line outputs. All data is SRC'd to 96kHz in this mode, and processed in the DAP at 96kHz.

The 176.4-kHz to 192-kHz configuration supports four channels of signal processing with two channels passed through (or derived from the three processed channels).

To support efficiently the processing requirements of both multichannel 32-kHz to 96-kHz data and the 6-channel 176.4-kHz and 192-kHz data, the TAS5548 has separate audio-processing features for 32-kHz to 96-kHz data rates and for 176.4 kHz and 192 kHz. See Table 6 for a summary of TAS5548 processing feature sets.

7.4.7.2 TAS5548 Audio-Processing Feature Sets

The audio processing architecture of the TAS5548 DAP for normal and double speed configurations is shown below.

7.4.10.1 Digital Audio Processor (DAP) Arithmetic Unit

The digital audio processor (DAP) arithmetic unit is a fixed-point computational engine consisting of an arithmetic unit and data and coefficient memory blocks.

The DAP arithmetic unit is used to implement all firmware functions - loudness compensation, bass and treble processing, dynamic range control, channel filtering, input and output mixing.

Figure 26 shows the data word structure of the DAP arithmetic unit. Four bits of overhead or guard bits are provided at the upper end of the 32-bit DAP word, and 4 bits of computational precision or noise bits are provided at the lower end of the 32-bit word. The incoming digital audio words are all positioned with the most significant bit abutting the 4-bit overhead/guard boundary. The sign bit in bit 31 indicates that all incoming audio samples are treated as signed data samples.

Figure 26. DAP Arithmetic Unit Data Word Structure

The arithmetic engine is a 32-bit (9.23 format) processor consisting of a general-purpose 60-bit arithmetic logic unit and function-specific arithmetic blocks. Multiply operations (excluding the function-specific arithmetic blocks) always involve 32-bit (9.23) DAP words and 28-bit (5.23) coefficients (usually I2C programmable coefficients). If a group of products are to be added together, the 60-bit product of each multiplication is applied to a 60-bit adder, where a DSP-like multiply-accumulate (MAC) operation takes place. Biquad filter computations use the MAC operation to maintain precision in the intermediate computational stages.

To maximize the linear range of the 76-bit ALU, saturation logic is not used. In MAC computations, intermediate overflows are permitted, and it is assumed that subsequent terms in the computation flow will correct the overflow condition. The biquad filter structure used in the TAS5548 is the “direct form I” structure and has only one accumulation node (for an example, see ). With this type of structure, intermediate overflow are allowable as long as the designer of the filters has assured that the final output will bounded and not overflow. Figure 27 is an example, using 8-bit arithmetic for ease of illustration, of a bounded computation that experiences intermediate overflow condition.

The DAP memory banks include a dual port data RAM for storing intermediate results, a coefficient RAM, and a fixed program ROM. Only the coefficient RAM, assessable via the I2C bus, is available to the user.

Figure 27. DAP ALU Operation With Intermediate Overflow

7.4.10.2 28-Bit 5.23 Number Format

All mixer gain coefficients are 28-bit coefficients using a 5.23 number format. Numbers formatted as 5.23 numbers have 5 bits to the left of the binary point and 23 bits to the right of the binary point. This is shown in Figure 28.

Figure 28. 5.23 Format

The decimal value of a 5.23 format number can be found by following the weighting shown in Figure 29. If the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the most significant bit is a logic 1, then the number is a negative number. In this case, every bit must be inverted, a 1 added to the result, and then the weighting shown in Figure 29 applied to obtain the magnitude of the negative number.

Figure 29. Conversion Weighting Factors—5.23 Format to Floating Point

Gain coefficients, entered via the I²C bus, must be entered as 32-bit binary numbers. The format of the 32-bit number (4-byte or 8-digit hexadecimal number) is shown in Figure 30.

Figure 30. Alignment of 5.23 Coefficient in 32-Bit I²C Word

As Figure 30 shows, the hexadecimal (hex) value of the integer part of the gain coefficient cannot be concatenated with the hex value of the fractional part of the gain coefficient to form the 32-bit I²C coefficient. The reason is that the 28-bit coefficient contains 5 bits of integer, and thus the integer part of the coefficient occupies all of one hex digit and the most significant bit of the second hex digit. In the same way, the fractional part occupies the lower three bits of the second hex digit, and then occupies the other five hex digits (with the eighth digit being the zero-valued most significant hex digit).

7.4.10.3 TAS5548 Audio Processing

The TAS5548 digital audio processing is designed so that noise produced by filter operations is maintained below the smallest signal amplitude of interest, as shown in Figure 31. The device achieves this low noise level by increasing the precision of the signal representation substantially above the number of bits that are absolutely necessary to represent the input signal.

Similarly, the TAS5548 carries additional precision in the form of overflow bits to permit the value of intermediate calculations to exceed the input precision without clipping. The TAS5548's advanced digital audio processor achieves both of these important performance capabilities by using a high-performance digital audio-processing architecture with a 32-bit data path, 28-bit filter coefficients, and a 60-bit accumulator.

Figure 31. TAS5548 Digital Audio Processing

Table 7. Contents of One 20-Byte Biquad Filter Register (Default = All-Pass)

Table 8. Bass and Treble Filter Selections

Table 9. Default Loudness Compensation Parameters

7.4.15.1 Loudness Example

Problem: Due to the Fletcher-Munson phenomena, compensation for low-frequency attenuation near 60 Hz is desirable. The TAS5548 provides a loudness transfer function with EQ gain = 6, EQ center frequency = 60 Hz, and EQ bandwidth = 60 Hz.

Solution: Using Texas Instruments TAS5548 GUI tool (downloadable from ti.com), Matlab™, or other signal-processing tool, develop a loudness function with the parameters listed in Table 10.

See Figure 35 for the resulting loudness function at different gains.

Figure 35. Loudness Example Plots

Table 11. DRC Recommended Changes From TAS5548 Defaults

7.4.16.1 DRC Implementation

The three elements comprising the DRC include: (1) an rms estimator, (2) a compression/expansion coefficient computation engine, and (3) an attack/decay controller.

• RMS estimator—This DRC element derives an estimate of the rms value of the audio data stream into the DRC. For the DRC block shared by Ch1 and Ch2, two estimates are computed—an estimate of the Ch1 audio data stream into the DRC, and an estimate of the Ch2 audio data stream into the DRC. The outputs of the two estimators are then compared, sample-by-sample, and the larger-valued sample is forwarded to the compression/expansion coefficient computation engine.              
  Two programmable parameters, ae and (1 – ae), set the effective time window over which the rms estimate is made. For the DRC block shared by Ch1 and Ch2, the programmable parameters apply to both rms estimators. The time window over which the rms estimation is computed can be determined by:
Equation 1.
a. Care should be taken when calculating the time window for 192kHz content. Please use 96kHz as the sampling frequency for 96kHz AND 192kHz, as the TAS5548 uses a digital decimator to do all DAP processing at 96kHz.
b. ae = energy time
• Compression/expansion coefficient computation—This DRC element converts the output of the rms estimator to a logarithmic number, determines the region where the input resides, and then computes and outputs the appropriate coefficient to the attack/decay element. Seven programmable parameters, T1, T2, O1, O2, k0, k1, and k2, define the three compression/expansion regions implemented by this element.
• Attack/decay control—This DRC element controls the transition time of changes in the coefficient computed in the compression/expansion coefficient computation element. Four programmable parameters define the operation of this element. Parameters ad and (1 – ad) set the decay or release time constant to be used for volume boost (expansion). Parameters aa and (1 – aa) set the attack time constant to be used for volume cuts. The transition time constants can be determined by:

Equation 2.

a. aa = attack time

b. ad - decay time

7.4.16.2 Compression/Expansion Coefficient Computation Engine Parameters

Seven programmable parameters are assigned to each DRC block: two threshold parameters—T1 and T2, two offset parameters—O1 and O2, and three slope parameters—k0, k1, and k2. The threshold parameters establish the three regions of the DRC transfer curve, the offsets anchor the transfer curve by establishing known gain settings at the threshold levels, and the slope parameters define whether a given region is a compression or an expansion region.

T2 establishes the boundary between the high-volume region and the mid-volume region. T1 establishes the boundary between the mid-volume region and the low-volume region. Both thresholds are set in logarithmic space, and which region is active for any given rms estimator output sample is determined by the logarithmic value of the sample.

Threshold T2 serves as the fulcrum or pivot point in the DRC transfer function. O2 defines the boost (> 0 dB) or cut (< 0 dB) implemented by the DRC-derived gain coefficient for an rms input level of T2. If O2 = 0 dB, the value of the derived gain coefficient is 1 (0x0080 0000 in 5.23 format). k2 is the slope of the DRC transfer function for rms input levels above T2, and k1 is the slope of the DRC transfer function for rms input levels below T2 (and above T1). The labeling of T2 as the fulcrum stems from the fact that there cannot be a discontinuity in the transfer function at T2. The user can, however, set the DRC parameters to realize a discontinuity in the transfer function at the boundary defined by T1. If no discontinuity is desired at T1, the value for the offset term O1 must obey the following equation.

Equation 3.

T1 and T2 are the threshold settings in dB, k1 is the slope for region 1, and O2 is the offset in dB at T2. If the user chooses to select a value of O1 that does not obey the above equation, a ×discontinuity at T1 is realized.

Decreasing in volume from T2, the slope k1 remains in effect until the input level T1 is reached. If, at this input level, the offset of the transfer function curve from the 1 : 1 transfer curve does not equal O1, there is a discontinuity at this input level as the transfer function is snapped to the offset called for by O1. If no discontinuity is wanted, O1 and/or k1 must be adjusted so that the value of the transfer curve at input level T1 is offset from the 1 : 1 transfer curve by the value O1. The examples that follow illustrate both continuous and discontinuous transfer curves at T1.

Decreasing in volume from T1, starting at offset level O1, slope k0 defines the compression/expansion activity in the lower region of the DRC transfer curve.

7.4.16.2.1 Threshold Parameter Computation

For thresholds,

T_dB = –6.0206T_INPUT= –6.0206T_{SUB_ADDRESS_ENTRY}

If, for example, it is desired to set T1 = –64 dB, then the subaddress entry required to set T1 to –64 dB is:

T1 is entered as a 32-bit number in 9.23 format. Therefore:

T1 = 10.63	= 0 1010.1010 0001 0100 0111 1010 111
	= 0x0550 A3D7 in 9.23 format

7.4.16.2.2 Offset Parameter Computation

The offsets set the boost or cut applied by the DRC-derived gain coefficient at the threshold point. An equivalent statement is that offsets represent the departure of the actual transfer function from a 1 : 1 transfer at the threshold point. Offsets are 9.23 Formatted, 32bit logarithmic numbers. They are computed by the following equation:

Gains or boosts are represented as negative numbers; cuts or attenuations are represented as positive numbers. For example, to achieve a boost of 21 dB at threshold T1, the I²C coefficient value entered for O1 must be:

7.4.16.2.3 Slope Parameter Computation

In developing the equations used to determine the subaddress of the input value required to realize a given compression or expansion within a given region of the DRC, the following convention is adopted.

where

If the DRC realizes an output increase of n dB for every dB increase in the rms value of the audio into the DRC, a 1 : n expansion is being performed. If the DRC realizes a 1-dB increase in output level for every n-dB increase in the rms value of the audio into the DRC, an n : 1 compression is being performed.

where

For n : 1 compression, the slope k can be found by: 

In both expansion (1 : n) and compression (n : 1), n is implied to be greater than 1. Thus, for expansion:

k = n – 1 means k > 0 for n > 1. Likewise, for compression, means –1 < k < 0 for n > 1. Thus, it appears that k must always lie in the range k > –1.

The DRC imposes no such restriction and k can be programmed to values as negative as –15.999. To determine what results when such values of k are entered, it is first helpful to note that the compression and expansion equations for k are actually the same equation. For example, a 1 : 2 expansion is also a 0.5 : 1 compression.

As can be seen, the same value for k is obtained either way. The ability to choose values of k less than –1 allows the DRC to implement negative-slope transfer curves within a given region. Negative-slope transfer curves are usually not associated with compression and expansion operations, but the definition of these operations can be expanded to include negative-slope transfer functions. For example, if k = –4

With k = –4, the output decreases 3 dB for every 1 dB increase in the rms value of the audio into the DRC. As the input increases in volume, the output decreases in volume.

7.4.19.1 Left Total/Right Total (Lt/Rt)

Lt/Rt is a downmix suitable for decoding with a Dolby Pro Logic upmixer to obtain 5.1 channels again. Lt/Rt is also suitable for stereophonic sound playback on a hi-fi or on headphones.

Equation 6.

where Ls and Rs are phase shifted 90°

7.4.19.2 Left Only/Right Only (Lo/Ro)

Lo/Ro is a downmix suitable when mono compatibility is required. Lo/Ro destroys front/rear channel separation information and thus a Dolby Pro Logic upmixer will not be able to properly extract 5.1 channels again.

Equation 7.

where att = –3 dB, –6 dB, –9 dB or 0 dB

7.4.21.1 Channel Configuration

These registers control the TAS5548 response to back end errors.

Table 12. Description of the Channel Configuration Registers (0x05 to 0x0C)

7.4.21.2 Headphone Configuration Registers

The headphone configuration controls are identical to the speaker configuration controls. The headphone configuration control settings are used in place of the speaker configuration control settings for channels 1 and 2 when the headphones are selected. However, only one configuration setting for headphones is used, and it is the default setting, that is, in headphone mode 0x05 and 0x06 settings are fixed in default.

7.4.21.3 Audio System Configurations

The TAS5548 can be configured to comply with various audio systems: 5.1-channel system, 6-channel system, 7.1-channel system, and 8-channel system.

The audio system configuration is set in the general control register (0xE0). Bits D31–D4 must be zero and D0 is do not care.

D3–D1 must be configured for the audio system in the application, as shown in Table 13.

7.4.21.4 Recovery from Clock Error

The TAS5548 can be set either to perform a volume ramp up during the recovery sequence of a clock error or simply to come up in the last state (or desired state if a volume or tone update was in progress). This feature is enabled via I²C system control register 0x03.

7.4.21.5 Power-Supply Volume-Control Enable

The power-supply volume control (PSVC) can be enabled and disabled via I²C register 0xE0. The subwoofer PWM output is always controlled by the PSVC. When using PSVC the subwoofer cannot be used as lineout.

7.4.21.6 Volume and Mute Update Rate

The TAS5548 has fixed soft volume and mute ramp durations. The ramps are linear. The soft volume and mute ramp rates are adjustable by programming the I²C register 0xD0 for the appropriate number of steps to be 512, 1024, or 2048. The update is performed at a fixed rate regardless of the sample rate.

• In normal speed, the update rate is 1 step every 4/f_S seconds.
• In double speed, the update is 1 step every 8/f_S seconds.
• In quad speed, the update is 1 step every 16/f_S seconds.

Because of processor loading, the update rate can increase for some increments by one step every 1/f_S to 3/f_S. However, the variance of the total time to go from 18 dB to mute is less than 25%.

7.4.21.7 Modulation Index Limit

PWM modulation is a linear function of the audio signal. When the audio signal is 0, the PWM modulation is 50%. When the audio signal increases toward full scale, the PWM modulation increases toward 100%. For negative signals, the PWM modulations fall below 50% toward 0%.

However, the maximum possible modulation does have a limit. During the off time period, the power stage connected to the TAS5548 output needs to get ready for the next on-time period. The maximum possible modulation is then set by the power stage requirements. The default modulation index limit setting is 93.7%; however, some power stages may require a lower modulation limit. See the applicable power stage data sheet for details on setting the modulation index limit. The default setting of 93.7% can be changed in the modulation index register (0x16).

7.4.22.1 192kHz Native Processing Mode

The TAS5548 ASRC defaults to 96kHz at startup. This means all DAP processing and filter calculations should be based on 96kHz sample rate.

However, the TAS5548 is also capable of processing content at 192kHz (with a reduced channel count).

To enable 192kHz native mode

• Write to 0xC5 ASRC Mode Control
• Set D20 = 1 (Serial clock output sampling rate is the internal sampling rate)
• Set D1:0 = 01 (192kHz Sampling Rate)
• 0xC5 = 0011 0001

DAP processing and filter calculations should be based on 192kHz sample rate. This mode should be used with an incoming I2S rate of 192kHz

7.4.22.2 PLL Operation

The TAS5548 uses two internal clocks generated by two internal phase-locked loops (PLLs), the digital PLL (DPLL) and the analog PLL (APLL). The APLL provides the reference clock for the PWM. The DPLL provides the reference clock for the digital audio processor and the control logic.

The XTAL input provides the input reference clock for the APLL. The external crystal provides a time base to support a number of operations, including the detection of the MCLK ratio, the data rate, and clock error conditions. The internal oscillator time base provides a constant rate for all controls and signal timing.

7.5.1.1 General I²C Operation

The I²C bus employs two signals—SDA (data) and SCL (clock)—to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on SDA while the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 40. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The TAS5548 holds SDA low during the acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the high level for the bus.

Figure 40. Typical I²C Sequence

The number of bytes that can be transmitted between start and stop conditions is unlimited. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 40.

The 7-bit address for the TAS5548 is 0011011. When the R/W bit is added as the LSB, the I²C write address is 0x36 and the I²C read address is 0x37.

7.5.1.2 Single- and Multiple-Byte Transfers

The serial-control interface supports both single-byte and multiple-byte read/write operations for status registers and the general control registers associated with the PWM. However, for the DAP data processing registers, the serial-control interface supports only multiple-byte (four-byte) read/write operations.

During multiple-byte read operations, the TAS5548 responds with data, a byte at a time, starting at the subaddress assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does not contain 32 bits, the unused bits are read as logic 0.

During multiple-byte write operations, the TAS5548 compares the number of bytes transmitted to the number of bytes that are required for each specific subaddress. If a write command is received for a biquad subaddress, the TAS5548 expects to receive five 32-bit words. If fewer than five 32-bit data words have been received when a stop command (or another start command) is received, the data received is discarded. Similarly, if a write command is received for a mixer coefficient, the TAS5548 expects to receive one 32-bit word.

Supplying a subaddress for each subaddress transaction is referred to as random I²C addressing. The TAS5548 also supports sequential I²C addressing. For write transactions, if a subaddress is issued followed by data for that subaddress and the 15 subaddresses that follow, a sequential I²C write transaction has taken place, and the data for all 16 subaddresses is successfully received by the TAS5548. For I²C sequential write transactions, the subaddress then serves as the start address and the amount of data subsequently transmitted, before a stop or start is transmitted, determines how many subaddresses are written. As is true for random addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted; only the incomplete data is discarded.

7.5.1.3 Single-Byte Write

As shown in Figure 41, a single-byte, data-write transfer begins with the master device transmitting a start condition followed by the I²C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I²C device address and the read/write bit, the TAS5548 device responds with an acknowledge bit. Next, the master transmits the address byte or bytes corresponding to the TAS5548 internal memory address being accessed. After receiving the address byte, the TAS5548 again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5548 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte, data-write transfer.

Figure 41. Single-Byte Write Transfer

7.5.1.4 Multiple-Byte Write

A multiple-byte, data-write transfer is identical to a single-byte, data-write transfer except that multiple data bytes are transmitted by the master device to TAS5548, as shown in Figure 42. After receiving each data byte, the TAS5548 responds with an acknowledge bit.

Figure 42. Multiple-Byte Write Transfer

7.5.1.5 Incremental Multiple-Byte Write

The I²C supports a special mode which permits I²C write operations to be broken up into multiple data write operations that are multiples of four data bytes. These are 6-byte, 10-byte, 14-byte, 18-byte, etc., write operations that are composed of a device address, read/write bit, subaddress, and any multiple of four bytes of data. This permits the system to write large register values incrementally without blocking other I²C transactions.

This feature is enabled by the append subaddress function in the TAS5548. This function enables the TAS5548 to append four bytes of data to a register that was opened by a previous I²C register write operation but has not received its complete number of data bytes. Because the length of the long registers is a multiple of four bytes, using four-byte transfers has only an integral number of append operations.

When the correct number of bytes has been received, the TAS5548 begins processing the data.

The procedure to perform an incremental multibyte-write operation is as follows:

1. Start a normal I²C write operation by sending the device address, write bit, register subaddress, and the first four bytes of the data to be written. At the end of that sequence, send a stop condition. At this point, the register has been opened and accepts the remaining data that is sent by writing four-byte blocks of data to the append subaddress (0xFE).
2. At a later time, one or more append data transfers are performed to incrementally transfer the remaining number of bytes in sequential order to complete the register write operation. Each of these append operations is composed of the device address, write bit, append subaddress (0xFE), and four bytes of data followed by a stop condition.
3. The operation is terminated due to an error condition, and the data is flushed:
   1. If a new subaddress is written to the TAS5548 before the correct number of bytes are written.
   2. If more or fewer than four bytes are data written at the beginning or during any of the append operations.
   3. If a read bit is sent.

7.5.1.6 Single-Byte Read

As shown in Figure 43, a single-byte, data-read transfer begins with the master device transmitting a start condition followed by the I²C device address and the read/write bit. For the data-read transfer, both a write and then a read are actually performed. Initially, a write is performed to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit is a 0. After receiving the TAS5548 address and the read/write bit, the TAS5548 responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the TAS5548 address and the read/write bit again. This time the read/write bit is a 1, indicating a read transfer. After receiving the TAS5548 address and the read/write bit, the TAS5548 again responds with an acknowledge bit. Next, the TAS5548 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte, data-read transfer.

Figure 43. Single-Byte Read Transfer

7.5.1.7 Multiple-Byte Read

A multiple-byte, data-read transfer is identical to a single-byte, data-read transfer except that multiple data bytes are transmitted by the TAS5548 to the master device, as shown in Figure 44. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte.

Figure 44. Multiple-Byte Read Transfer

7.6.2.1 General Status Register 0 (0x01)

7.6.2.2 Error Status Register (0x02)

Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if there are any persistent errors. Bits D7-D4 are reserved.

7.6.2.3 System Control Register 1 (0x03)

Bits D1 and D0 are Reserved.

7.6.2.4 System Control Register 2 (0x04)

Bit D3 is reserved.

7.6.2.5 Channel Configuration Control Registers (0x05–0x0C)

Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, and 0x0C, respectively.

7.6.2.6 Headphone Configuration Control Register (0x0D)

Bit D0 is don't care.

7.6.2.7 Serial Data Interface Control Register (0x0E)

Nine serial modes can be programmed via the I²C interface.

7.6.2.8 Soft Mute Register (0x0F)

Do not use this register if using the remapped output mixer configuration.

7.6.2.9 Energy Manager Status Register (0x10)

These bits are sticky and will be cleared only when a '0' is written into these bits through I²C interface.

7.6.2.10 Automute Control Register (0x14)

Automute threshold are in dB with respect to a full-scale input signal. The thresholds are approximate.

7.6.2.11 Output Automute PWM Threshold and Back-End Reset Period Register (0x15)

For more information on how to use this register, see Automute and Mute Channel Controls,

PWM Automute is in dB with respect to Input Automute Threshold. The Thresholds are approximate.

7.6.2.12 Modulation Index Limit Register (0x16, 0x17, 0x18, 0x19)

Note that some power stages require a lower modulation limit than the default of 93.7%. Contact Texas Instruments for more details about the requirements for a particular power stage.

There are 512 DCLK Cycles per PWM frame.

7.6.2.13 AD Mode - 8 Interchannel Channel Delay and Global Offset Registers (0x1B to 0x23)

Interchannel delay is used to distribute the switching current of each channel, to ease the peak power draw on the PSU. It's also used to control the intermodulation between the channels, therefore improving THD in some cases.

DCLK is the oversampling clock of the PWM.

DCLK on the TAS5548 will be constant, unless some AM avoidance modes are used.

Each channel can have its channel delay set between -128 to +124. (4 DCLK steps value (-32 to +31 over 5 bits))

Channels 0, 1, 2, 3, 4, 5, 6, 7 are mapped into (0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22) with bits D[7:2] used to program individual DCLK delay. Bit D[1:0] are reserved in each register.

A Global offset can be used in register 0x23

7.6.2.14 Special Low Z and Mid Z Ramp/Stop Period (0x24)

This is also the delay period for delayed start/stop with legacy LowZ sequences. If register 0x25 is programmed for special LowZ sequence, the time above is the PWM ramp up period. If it is programmed for MidZ, the time above is the PWM stop period.

7.6.2.15 PWM and EMO Control Register (0x25)

7.6.2.16 Individual Channel Shutdown (0x27)

Individual channel shutdown register should be written prior to bringing system out of shutdown using reg 0x03 (Exit Shutdown).

7.6.2.17 Input Mux Registers (0x30, 0x31, 0x32, 0x33)

7.6.2.18 PWM Mux Registers (0x34, 0x35, 0x36, 0x37)

7.6.2.19 BD Mode and Ternary - 8 Interchannel Channel Delay (0x38 to 0x3F)

Interchannel delay is used to distribute the switching current of each channel, to ease the peak power draw on the PSU. It's also used to control the intermodulation between the channels, therefore improving THD in some cases.

DCLK is the oversampling clock of the PWM.

DCLK on the TAS5548 will be constant, unless some AM avoidance modes are used.

Each channel can have its channel delay set between -128 to +124. (4 DCLK steps value (-32 to +31 over 5 bits))

Channels 0, 1, 2, 3, 4, 5, 6, 7 are mapped into (0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F) with bits D[7:2] used to program individual DCLK delay. Bit D[1:0] are reserved in each register.

7.6.2.20 Input Mixer Registers, Channels 1–8 (0x41–0x48)

Input mixers 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, and 0x48, respectively.

Each gain coefficient is in 28-bit (5.23) format, so 0x80 0000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits reserved. For eight gain coefficients, the total is 32 bytes.

There is no negative value available. The mixer cannot phase invert.

Bold indicates the one channel that is passed through the mixer.

7.6.2.21 Bass Mixer Registers (0x49–0x50)

Registers 0x49–0x50 provide configuration control for bass mangement.

Each gain coefficient is in 28-bit (5.23) format, so 0x80 0000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits reserved.

There is no negative value available. The mixer cannot phase invert.

7.6.2.22 Biquad Filter Register (0x51–0x88)

Each gain coefficient is in 28-bit (5.23) format, so 0x80 0000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits not used.

7.6.2.23 Bass and Treble Register, Channels 1–8 (0x89–0x90)

Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, and 0x90, respectively. Eight bytes are written for each channel. Each gain coefficient is in 28-bit (5.23) format, so 0x80 0000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits reserved.

7.6.2.24 Loudness Registers (0x91–0x95)

7.6.2.25 DRC1 Control Register CH1-7 (0x96) – Write

DRC Control selects which channels contribute to the expansion/compression evaluation using DRC1. The evaluation is global such that if one signal forces compression all DRC1 signals will be in compression.