ASEL_EMO2 |
10 |
DIO |
|
Pullup |
I2C Address Select. Address will 0X34/0X36 with the value of pin being "0' or "1" during de-assertion of reset. Can be programmed to be an output (as energy manager output for subwoofer) |
AVDD |
9 |
P |
|
|
Analog supply (3.3 V) for PLL. |
AVDD_PWM |
50 |
P |
|
|
3.3-V analog power supply for PWM. This terminal can be connected to the same power source used to drive power terminal DVDD; but to achieve low PLL jitter, this terminal should be bypassed to AVSS_PWM with a 0.1-μF low-ESR capacitor. |
AVSS |
5 |
P |
|
|
Analog ground |
AVSS_PWM |
51 |
P |
|
|
Analog ground for PWM. Must have direct return Cu path to analog 3.3V supply for optimized performance. |
BKND_ERR |
34 |
DI |
|
Pullup |
Active-low. A back-end error sequence is generated by applying logic low to this terminal. The BKND_ERR results in no change to I2C parameters, with all H-bridge drive signals going to a hard-mute state (Non PWM Switching). |
DVDD1 |
35 |
P |
|
|
3.3-V digital power supply. (It is recommended that decoupling capacitors of 0.1 μF and 10 μF be mounted close to this pin). |
DVDD2 |
14 |
P |
|
|
3.3-V digital power supply for PWM. (It is recommended that decoupling capacitors of 0.1 μF and 10 μF be mounted close to this pin). |
DVSS1 |
36 |
P |
|
|
Digital ground 1 |
DVSS2 |
13 |
P |
|
|
Digital ground 2 |
EMO1 |
15 |
DO |
|
|
Energy Manger Output interrupt - Asserted high when threshold is exceeded. |
HP_SEL |
17 |
DI |
5 V |
Pullup |
Headphone/speaker selector. When a logic low is applied, the headphone is selected (speakers are off). When a logic high is applied, speakers are selected (headphone is off). |
LRCLK |
22 |
DI |
5 V |
Pulldown |
Serial-audio data left/right clock (sampling-rate clock) |
LRCLKO / LRCKIN_2 |
31 |
DIO |
5V |
Pulldown |
LRCLK for I2S OUT. Can also be used as LRCKIN_2 (I2S Input for SDIN2_x and SRC Bank 2) |
MLCK |
11 |
DI |
|
|
3.3-V master clock input. The input frequency of this clock can range from 2 MHz to 50 MHz. |
MUTE |
19 |
DI |
5 V |
Pullup |
Soft mute of outputs, active-low (muted signal = a logic low, normal operation = a logic high). The mute control provides a noiseless volume ramp to silence. Releasing mute provides a noiseless ramp to previous volume. |
OSCRES |
12 |
DO |
|
18k resistor to GND |
Oscillator resistor (1% tolerance). |
PDN |
18 |
DI |
5 V |
Pullup |
Power down, active-low. PDN powers down all logic and stops all clocks whenever a logic low is applied. The I2C parameters are preserved through a power-down cycle, as long as RESET is not active. |
PLL_FLTM |
6 |
AIO |
|
|
PLL negative filter. |
PLL_FLTP |
7 |
AIO |
|
|
PLL positive filter. |
PSVC/MCLKO |
33 |
DO |
|
|
Power-supply volume control PWM output or MCKO for external ADC (SDIN5 Source) |
PWM_HPM_L |
1 |
DO |
|
|
PWM left-channel headphone (differential –) |
PWM_HPM_R |
3 |
DO |
|
|
PWM right-channel headphone (differential –) |
PWM_HPP_L |
2 |
DO |
|
|
PWM left-channel headphone (differential +) |
PWM_HPP_R |
4 |
DO |
|
|
PWM right-channel headphone (differential +) |
PWM_M_1 |
38 |
DO |
|
|
PWM 1 output (differential –) |
PWM_M_2 |
40 |
DO |
|
|
PWM 2 output (differential –) |
PWM_M_3 |
42 |
DO |
|
|
PWM 3 output (differential –) |
PWM_M_4 |
44 |
DO |
|
|
PWM 4 output (differential –) |
PWM_M_5 |
53 |
DO |
|
|
PWM 5 output (lineout L) (differential –) |
PWM_M_6 |
55 |
DO |
|
|
PWM 6 output (lineout R) (differential –) |
PWM_M_7 |
46 |
DO |
|
|
PWM 7 output (differential –) |
PWM_M_8 |
48 |
DO |
|
|
PWM 8 output (differential –) |
PWM_P_1 |
39 |
DO |
|
|
PWM 1 output (differential +) |
PWM_P_2 |
41 |
DO |
|
|
PWM 2 output (differential +) |
PWM_P_3 |
43 |
DO |
|
|
PWM 3 output (differential +) |
PWM_P_4 |
45 |
DO |
|
|
PWM 4 output (differential +) |
PWM_P_5 |
54 |
DO |
|
|
PWM 5 output (lineout L) (differential +) |
PWM_P_6 |
56 |
DO |
|
|
PWM 6 output (lineout R) (differential +) |
PWM_P_7 |
47 |
DO |
|
|
PWM 7 output (differential +) |
PWM_P_8 |
49 |
DO |
|
|
PWM 8 output (differential +) |
RESET |
16 |
DI |
5 V |
Pullup |
System reset input, active-low. A system reset is generated by applying a logic low to this terminal. RESET is an asynchronous control signal that restores the TAS5558 to its default conditions, sets the valid output low, and places the PWM in the hard-mute state (Non PWM Switching). Master volume is immediately set to full attenuation. On the release of RESET, if PDN is high, the system performs a 4- to 5-ms device initialization and sets the volume at mute. |
SCL |
21 |
DI |
5 V |
|
I2C serial-control clock input/output |
SCLK |
23 |
DI |
5 V |
Pulldown |
Serial-audio data clock (shift clock) input |
SCLKO / SCLKIN_2 |
30 |
DIO |
5V |
Pulldown |
Serial data clock out. I2S bit clock out. Can also be used as SCLKIN_2 (I2S Input for SDIN2_x and SRC Bank 2) |
SDA |
20 |
DIO |
5 V |
|
I2C serial-control data-interface input/output |
SDIN1 |
24 |
DI |
5 V |
Pulldown |
Serial-audio data bank 1 input 1 is one of the serial-data input ports and goes into the 1st SRC Bank. Four discrete (stereo) data formats and is capable of inputting data at 64 fS. |
SDIN2 |
25 |
DI |
5 V |
Pulldown |
Serial-audio data bank 1 input 2 is one of the serial-data input ports and goes into the 1st SRC Bank. Four discrete (stereo) data formats and is capable of inputting data at 64 fS. |
SDIN2-1 |
26 |
DI |
5 V |
Pulldown |
Serial-audio data bank 2 input 1 is one of the serial-data input ports and goes into the 2nd SRC Bank. Four discrete (stereo) data formats and is capable of inputting data at 64 fS. |
SDIN2-2 |
27 |
DI |
5 V |
Pulldown |
Serial-audio data bank 2 input 2 is one of the serial-data input ports and goes into the 2nd SRC Bank. Four discrete (stereo) data formats and is capable of inputting data at 64 fS. |
SDOUT / SDIN5 |
29 |
|
|
|
I2S data out or SDIN5 (must be sync'd to post SRC rate). Usually used for Microphone ADC Input |
TEST |
32 |
DI |
|
|
Test mode active high. In normal mode tie this to digital ground. |
VALID |
37 |
DO |
|
|
Output indicating validity of PWM outputs, active-high |
VR_DIG |
28 |
P |
|
|
Voltage reference for 1.8-V digital core supply. A pinout of the internally regulated 1.8-V power used by digital core logic. A 4.7-μF low-ESR capacitor should be connected between this terminal and DVSS. This terminal must not be used to power external devices. |
VR_PWM |
52 |
P |
|
|
Voltage reference for 1.8-V digital PLL supply. A pinout of the internally regulated 1.8-V power used by digital PLL logic. A 0.1-μF low-ESR capacitor should be connected between this terminal and DVSS_CORE. This terminal must not be used to power external devices. |
VR_ANA |
8 |
P |
|
|
Voltage reference for 1.8-V PLL analog supply. A pinout of the internally regulated 1.8-V power used by PLL logic. A 0.1-µF low-ESR capacitor should be connected between this terminal and AVSS_PLL. This terminal must not be used to power external devices. |