SLES273B April   2013  – April 2015 TAS5558

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Dynamic Performance
    7. 6.7  SRC Performance
    8. 6.8  Timing I2C Serial Control Port Operation
    9. 6.9  Reset Timing (RESET)
    10. 6.10 Power-Down (PDN) Timing
    11. 6.11 Back-End Error (BKND_ERR)
    12. 6.12 Mute Timing (MUTE)
    13. 6.13 Headphone Select (HP_SEL)
    14. 6.14 Switching Characteristics - Clock Signals
    15. 6.15 Switching Characteristics - Serial Audio Port
    16. 6.16 Volume Control
    17. 6.17 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Audio Interface Control and Timing
        1. 7.3.1.1 Input I2S Timing
        2. 7.3.1.2 Left-Justified Timing
        3. 7.3.1.3 Right-Justified Timing
      2. 7.3.2 OUTPUT Serial Audio Output
      3. 7.3.3 I2S Master Mode
      4. 7.3.4 LRCKO and SCLKO
      5. 7.3.5 PWM Features
        1. 7.3.5.1 DC Blocking (High-Pass Filter Enable/Disable)
        2. 7.3.5.2 AM Interference Avoidance
      6. 7.3.6 TAS5558 Controls and Status
        1. 7.3.6.1 I2C Status Registers
          1. 7.3.6.1.1 General Status Register (0x01)
          2. 7.3.6.1.2 Error Status Register (0x02)
        2. 7.3.6.2 TAS5558 Pin Controls
          1. 7.3.6.2.1 Reset (RESET)
          2. 7.3.6.2.2 Power Down (PDN)
          3. 7.3.6.2.3 Back-End Error (BKND_ERR)
            1. 7.3.6.2.3.1 BKND_ERR and VALID
          4. 7.3.6.2.4 Speaker/Headphone Selector (HP_SEL)
          5. 7.3.6.2.5 Mute (MUTE)
          6. 7.3.6.2.6 Power-Supply Volume Control (PSVC)
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power Supply
      2. 7.4.2  Clock, PLL, and Serial Data Interface
      3. 7.4.3  Serial Audio Interface
      4. 7.4.4  I 2C Serial-Control Interface
      5. 7.4.5  Device Control
      6. 7.4.6  Energy Manager
      7. 7.4.7  Digital Audio Processor (DAP)
        1. 7.4.7.1 TAS5558 Audio-Processing Configurations
        2. 7.4.7.2 TAS5558 Audio-Processing Feature Sets
      8. 7.4.8  Pulse Width Modulation Schemes
      9. 7.4.9  TAS5558 DAP Architecture Diagrams
      10. 7.4.10 I 2C Coefficient Number Formats
        1. 7.4.10.1 Digital Audio Processor (DAP) Arithmetic Unit
        2. 7.4.10.2 28-Bit 5.23 Number Format
        3. 7.4.10.3 TAS5558 Audio Processing
      11. 7.4.11 Input Crossbar Mixer
      12. 7.4.12 Biquad Filters
      13. 7.4.13 Bass and Treble Controls
      14. 7.4.14 Volume, Automute, and Mute
      15. 7.4.15 Loudness Compensation
        1. 7.4.15.1 Loudness Example
      16. 7.4.16 Dynamic Range Control (DRC)
        1. 7.4.16.1 DRC Implementation
        2. 7.4.16.2 Compression/Expansion Coefficient Computation Engine Parameters
          1. 7.4.16.2.1 Threshold Parameter Computation
          2. 7.4.16.2.2 Offset Parameter Computation
          3. 7.4.16.2.3 Slope Parameter Computation
      17. 7.4.17 THD Manager
      18. 7.4.18 Downmix Algorithm and I2S Out
      19. 7.4.19 Stereo Downmixes/(or Fold-Downs)
        1. 7.4.19.1 Left Total/Right Total (Lt/Rt)
        2. 7.4.19.2 Left Only/Right Only (Lo/Ro)
      20. 7.4.20 Output Mixer
      21. 7.4.21 Device Configuration Controls
        1. 7.4.21.1 Channel Configuration
        2. 7.4.21.2 Headphone Configuration Registers
        3. 7.4.21.3 Audio System Configurations
          1. 7.4.21.3.1 Using Line Outputs in 6-Channel Configurations
        4. 7.4.21.4 Recovery from Clock Error
        5. 7.4.21.5 Power-Supply Volume-Control Enable
        6. 7.4.21.6 Volume and Mute Update Rate
        7. 7.4.21.7 Modulation Index Limit
      22. 7.4.22 Master Clock and Serial Data Rate Controls
        1. 7.4.22.1 192kHz Native Processing Mode
        2. 7.4.22.2 Supported MCLK Frequencies on the TAS5558
        3. 7.4.22.3 PLL Operation
        4. 7.4.22.4 MCLK Ratio Auto Detection
      23. 7.4.23 Bank Controls (ASRC Bypass only)
        1. 7.4.23.1 Manual Bank Selection
        2. 7.4.23.2 Automatic Bank Selection
          1. 7.4.23.2.1 Coefficient Write Operations While Automatic Bank Switch Is Enabled
        3. 7.4.23.3 Bank Set
        4. 7.4.23.4 Bank-Switch Timeline
        5. 7.4.23.5 Bank-Switching Example 1
    5. 7.5 Programming
      1. 7.5.1 I2C Serial-Control Interface (Slave Addresses 0x36)
        1. 7.5.1.1 General I2C Operation
        2. 7.5.1.2 Single- and Multiple-Byte Transfers
        3. 7.5.1.3 Single-Byte Write
        4. 7.5.1.4 Multiple-Byte Write
        5. 7.5.1.5 Incremental Multiple-Byte Write
        6. 7.5.1.6 Single-Byte Read
        7. 7.5.1.7 Multiple-Byte Read
    6. 7.6 Register Maps
      1. 7.6.1 Serial-Control I2C Register Summary
      2. 7.6.2 Serial-Control Interface Register Definitions
        1. 7.6.2.1  Clock Control Register (0x00)
        2. 7.6.2.2  General Status Register 0 (0x01)
        3. 7.6.2.3  Error Status Register (0x02)
        4. 7.6.2.4  System Control Register 1 (0x03)
        5. 7.6.2.5  System Control Register 2 (0x04)
        6. 7.6.2.6  Channel Configuration Control Registers (0x05-0x0C)
        7. 7.6.2.7  Headphone Configuration Control Register (0x0D)
        8. 7.6.2.8  Serial Data Interface Control Register (0x0E)
        9. 7.6.2.9  Soft Mute Register (0x0F)
        10. 7.6.2.10 Energy Manager Status Register (0x10)
        11. 7.6.2.11 Automute Control Register (0x14)
        12. 7.6.2.12 Output Automute PWM Threshold and Back-End Reset Period Register (0x15)
        13. 7.6.2.13 Modulation Index Limit Register (0x16, 0x17, 0x18, 0x19)
        14. 7.6.2.14 AD Mode - 8 Interchannel Channel Delay and Global Offset Registers (0x1B to 0x23)
        15. 7.6.2.15 Special Low Z and Mid Z Ramp/Stop Period (0x24)
        16. 7.6.2.16 PWM and EMO Control Register (0x25)
        17. 7.6.2.17 Individual Channel Shutdown (0x27)
        18. 7.6.2.18 Input Mux Registers (0x30, 0x31, 0x32, 0x33)
        19. 7.6.2.19 PWM Mux Registers (0x34, 0x35, 0x36, 0x37)
        20. 7.6.2.20 BD Mode and Ternary - 8 Interchannel Channel Delay (0x38 to 0x3F)
        21. 7.6.2.21 Bank-Switching Command Register (0x40) (TAS5558 + ASRC Bypass)
        22. 7.6.2.22 Input Mixer Registers, Channels 1-8 (0x41-0x48)
        23. 7.6.2.23 Bass Mixer Registers (0x49-0x50)
        24. 7.6.2.24 Biquad Filter Register (0x51-0x88)
        25. 7.6.2.25 Bass and Treble Register, Channels 1-8 (0x89-0x90)
        26. 7.6.2.26 Loudness Registers (0x91-0x95)
        27. 7.6.2.27 DRC1 Control Register CH1-7 (0x96) - Write
        28. 7.6.2.28 DRC2 Control Register CH8 (0x97) - Write Register
        29. 7.6.2.29 DRC1 Data Registers (0x98-0x9C)
        30. 7.6.2.30 DRC2 Data Registers (0x9D-0xA1)
        31. 7.6.2.31 DRC Bypass Registers (0xA2-0xA9)
        32. 7.6.2.32 Output Select and Mix Registers 8x2 (0x-0xAF)
        33. 7.6.2.33 8×3 Output Mixer Registers (0xB0-0xB1)
        34. 7.6.2.34 ASRC Registers (0xC3-C5)
        35. 7.6.2.35 Auto Mute Behavior (0xCC)
        36. 7.6.2.36 PSVC Volume Biquad Register (0xCF)
        37. 7.6.2.37 Volume, Treble, and Bass Slew Rates Register (0xD0)
        38. 7.6.2.38 Volume Registers (0xD1-0xD9)
        39. 7.6.2.39 Bass Filter Set Register (0xDA)
        40. 7.6.2.40 Bass Filter Index Register (0xDB)
        41. 7.6.2.41 Treble Filter Set Register (0xDC)
        42. 7.6.2.42 Treble Filter Index (0xDD)
        43. 7.6.2.43 AM Mode Register (0xDE)
        44. 7.6.2.44 PSVC Range Register (0xDF)
        45. 7.6.2.45 General Control Register (0xE0)
        46. 7.6.2.46 96kHz Dolby Downmix Coefficients (0xE3 to 0xE8)
        47. 7.6.2.47 THD Manager Configuration (0xE9 and 0xEA)
        48. 7.6.2.48 SDIN5 Input Mixer (0xEC-0xF3)
        49. 7.6.2.49 192kHZ Process Flow Output Mixer (0xF4-0xF7)
        50. 7.6.2.50 192kHz Dolby Downmix Coefficients (0xFB and 0xFC)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TAS5558 DVD Receiver Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Serial Port Master/Slave Configurations
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Device System Diagrams
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
    3. 8.3 Do’s and Don’ts
      1. 8.3.1 Frequency Scaling AM Avoidance
    4. 8.4 Initialization Set Up
      1. 8.4.1 Startup Register Writes to get Audio Functioning
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply
    2. 9.2 Energy Manager
    3. 9.3 Programming Energy Manager
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
Supply voltage, DVDD1 and DVDD2 –0.3 3.9 V
Supply voltage, AVDD and AVDD_PWM –0.3 3.9 V
Input voltage 3.3-V digital input –0.5 DVDD + 0.5 V
5-V tolerant(2) digital input –0.5 6
IIK Input clamp current (VI < 0 or VI > 1.8 V ±20 μA
IOK Output clamp current (VO < 0 or VO > 1.8 V) ±20 μA
TSTG Storage temperature range –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) 5-V tolerant signals are RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, SDIN4, SDA, and SCL.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±250 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±1000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over 0°C to 85°C
MIN NOM MAX UNIT
Digital supply voltage, DVDD1 and DVDD2 3 3.3 3.6 V
Analog supply voltage, AVDD and AVDD_PWM 3 3.3 3.6 V
VIH High‐level input voltage 3.3 V 2 V
5-V tolerant 2
1.8-V LVCMOS (XTL_IN) 1.26
VIL Low‐level input voltage 3.3 V 0.8 V
5-V tolerant 0.8
1.8-V (XTL_IN) 0.54
TA Operating ambient-air temperature 0 25 85 °C
TJ Operating junction temperature 0 105 °C

6.4 Thermal Information

THERMAL METRIC(1) TAS5558 UNIT
DCA (HTSSOP)
56 PINS
RθJA Junction-to-ambient thermal resistance 26.1 °C/W
RθJCtop Junction-to-case (top) thermal resistance 13.0
RθJB Junction-to-board thermal resistance 8.0
ψJT Junction-to-top characterization parameter 0.4
ψJB Junction-to-board characterization parameter 7.9
RθJCbot Junction-to-case (bottom) thermal resistance 0.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

At recommended operating conditions - 25 °C Operating Temp, 3.3V Power Supplies with 48kHz input data unless otherwise specified
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage 3.3-V TTL and 5-V tolerant IOH = –4 mA 2.4 V
1.8-V LVCMOS (XTL_OUT) IOH = –0.55 mA 1.44
VOL Low-level output voltage 3.3-V TTL and 5-V tolerant IOL = 4 mA 0.5 V
1.8-V LVCMOS (XTL_OUT) IOL = 0.75 mA 0.5
IOZ High-impedance output current 3.3-V TTL ±20 μA
IIL Low-level input current 3.3-V TTL VI = VIL ±1 μA
1.8-V LVCMOS (XTL_IN) VI = VIL ±1
5-V tolerant(2) VI = 0 V, DVDD = 3 V ±1
IIH High-level input current 3.3-V TTL VI = VIH ±1 μA
1.8-V LVCMOS (XTL_IN) VI = VIH ±1
5-V tolerant(2) VI = 5.5 V, DVDD = 3 V ±1
IDD Input supply current Digital supply voltage, DVDD Input fS = 48 kHz 220 mA
Power down 9
Analog supply voltage, AVDD Input fS = 48 kHz 8
Power down 8

6.6 Dynamic Performance

At recommended operating conditions at (25°C, 3.3V Power Supplies with 48kHz input data) unless otherwise noted.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
Dynamic range TAS5558 A-weighted (Test Range: 20Hz to 20kHz. fS = 96 kHz). 105 dB
Total harmonic distortion TAS5558 output (1kHz at -1dBFS) 0.01%
Frequency response 32-kHz to 96-kHz sample rates (Test Range 20Hz - 20kHz) ±0.1 dB
176.4, 192-kHz sample rates (Test Range 20Hz - 20kHz) ±0.2

6.7 SRC Performance

ATTRIBUTE VALUE
SRC Latency 102.53125/FSin + 36.46875/FSout
THD+N at 1kHz
Pass Band Ripple (worst case) ±0.05dB
SRC Channel Gain <1 (slightly lower to compensate for ripple)
Stop Band Attenuation 130dB
Pass Band Edge 0.425 FS-in
Stop Band Edge 0.575 FS-in

6.8 Timing I2C Serial Control Port Operation

Timing Characteristics for I2C Interface Signals over recommended operating conditions (unless otherwise noted)
STANDARD MODE FAST MODE UNIT
MIN MAX MIN MAX
fSCL SCL clock frequency 0 100 0 400 kHz
tHD-STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 0.6 μs
tLOW LOW period of the SCL clock 4.7 1.3 μs
tHIGH HIGH period of the SCL clock 4 0.6 μs
tSU-STA Setup time for repeated START 4.7 0.6 μs
tSU-DAT Data setup time 250 200 ns
tHD-DAT Data hold time 0 3.45 0 0.9 μs
tr Rise time of both SDA and SCL, see Figure 1 1000 20 + 0.1 Cb 500 ns
tf Fall time of both SDA and SCL, see Figure 1 300 20 + 0.1 Cb 300 ns
tSU-STO Setup time for STOP condition 4 0.6 μs
tBUF Bus free time between a STOP and START condition 4.7 1.3 μs
Cb Capacitive loads for each bus line 400 400 pF
VnL Noise margin at the LOW level for each connected device (including hysteresis) 0.1 × VDD 0.1 × VDD V
VnH Noise margin at the HIGH level for each connected device (including hysteresis) 0.2 × VDD 0.2 × VDD V

6.9 Reset Timing (RESET)

Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
tr(DMSTATE) Time to Non PWM Switching low 400 ns
tw(RESET) Pulse duration, RESET active, see Figure 3 400 None ns
tr(I2C_ready) Time to enable I2C 5 ms

6.10 Power-Down (PDN) Timing

Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
tp(DMSTATE) Time to Non PWM Switching low 650 μs
Number of MCLKs preceding the release of PDN, see Figure 4 5
tsu Device startup time 200 µs
Time to audio output 160 mS

6.11 Back-End Error (BKND_ERR)

Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
tw(ER) Pulse duration, BKND_ERR active, see Figure 5 350 None ns
tp(valid_low) Minimum amount of time that device asserts VALID low. <100 μs
tp(valid_high) I2C programmable to be between <1mS to 1.2 seconds (to avoid glitching with persistent BKND_ERR) –25 25 % of interval

6.12 Mute Timing (MUTE)

Control signal parameters over recommended operating conditions (unless otherwise noted). See Figure 6
PARAMETER MIN TYP MAX UNIT
td(VOL) Volume ramp time Defined by rate setting(1) ms

Note: No I2C commands during the volume ramp up/down.

6.13 Headphone Select (HP_SEL)

Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
tw(HP_SEL) Pulse duration, HP_SEL active, see Figure 7 165 ms
td(VOL) Soft volume update time Defined by rate setting(1) ms
t(SW) Switchover time 165 ms

6.14 Switching Characteristics - Clock Signals

PLL input parameters and external filter components over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fMCLKI Frequency, MCLK (1/tcyc2) 2 50 MHz
TAS5558: MCLK duty cycle 40% 50% 60%
TAS5558: MCLK minimum high time ≥2-V MCLK = 49.152 MHz, within the min and max duty cycle constraints 5 ns
TAS5558: MCLK minimum low time ≤0.8-V MCLK = 49.152 MHz, within the min and max duty cycle constraints 5 ns
LRCLK allowable drift before LRCLK reset 10 MCLKs
External PLL filter capacitors SMD 0603 X7R 100 nF
External PLL filter capacitors SMD 0603 X7R 10 nF
External PLL filter resistors SMD 0603, metal film, 1% 200 Ω
External VRA_PWM decoupling C14 SMD 0603 X7R 100 nF

6.15 Switching Characteristics - Serial Audio Port

Serial audio port slave mode over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSCLKIN SCLK input frequency CL = 30 pF 2.048 12.288 MHz
tsu1 Setup time, LRCLK to SCLK rising edge 10 ns
th1 Hold time, LRCLK from SCLK rising edge 10 ns
tsu2 Setup time, SDIN to SCLK rising edge 10 ns
th2 Hold time, SDIN from SCLK rising edge 10 ns
LRCLK frequency 32 48 192 kHz
SCLK rising edges between LRCLK rising edges 64 64 SCLK edges
SDOUT delay with respect to SCLK output (load = 30pF), see Figure 8 20 ns

6.16 Volume Control

Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Maximum attenuation before mute Individual volume, master volume, or a combination of both –127 dB
Maximum gain Individual volume, master volume 18 dB
Maximum volume before the onset of clipping 0-dB input, any modulation limit 0 dB
PSVC range PSVC enabled 12, 18, or 24 dB
PSVC rate fS
PSVC modulation Single sided
PSVC quantization 2048 Steps
PSVC PWM modulation limits PSVC range = 24 dB 6%
(120 : 2048)		 95%
(1944 : 2048)		 dB
TAS5558 scl_sdatiming_les238.gifFigure 1. SCL and SDA Timing
TAS5558 startstoptiming_les238.gifFigure 2. START and STOP Conditions Timing
TAS5558 t0029-04_les270.gifFigure 3. Reset Timing
TAS5558 t0030-03.gifFigure 4. Power-Down Timing
TAS5558 t0031-03.gifFigure 5. Error-Recovery Timing
TAS5558 t0032-02.gifFigure 6. Mute Timing
TAS5558 t0033-02.gifFigure 7. HP_SEL Timing
TAS5558 t0026-01.gifFigure 8. Slave Mode Serial Data Interface Timing

6.17 Typical Characteristics

TAS5558 D001_SLES270.gif
Figure 9. Frequency Response at 48 kHz Sampling Rate with -60 dB Input at 1 kHz
TAS5558 D003_SLES270.gif
Figure 11. Frequency Response at 44.1 kHz Sampling Rate with -60 dB Input at 1 kHz
TAS5558 D002_SLES270.gif
Figure 10. Frequency Response at 48 kHz Sampling Rate with 3 dB Input at 1 kHz
TAS5558 D004_SLES270.gif
Figure 12. Frequency Response at 44.1 kHz Sampling Rate with 3 dB Input at 1 kHz