7.3.1 Power Supplies

To facilitate system design, the TAS5630B needs only a 12-V supply in addition to the (typical) 50-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, for example, the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.

To provide outstanding electrical and acoustical characteristics, the PWM signal path, including gate drive and output stage, is designed as identical, independent half-bridges. For this reason, each half-bridge has separate gate drive supply pins (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X). Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the same 12-V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on the printed-circuit board (PCB) by RC filters (see Typical Application for details). These RC filters provide the recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power supply pins and decoupling capacitors must be avoided. (See SLAU287 for additional information.)

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range from 300 kHz to 400 kHz, it is recommended to use 33-nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle.

Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is decoupled with a 2.2-μF ceramic capacitor placed as close as possible to each supply pin. It is recommended to follow the PCB layout of the TAS5630B reference design. For additional information on recommended power supply and required components, see Typical Application.

The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50-V power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5630B is fully protected against erroneous power-stage turnon due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are non-critical within the specified range (see Recommended Operating Conditions).

7.3.2 System Power-Up and Power-Down Sequence

7.3.3 Error Reporting

The SD, OTW, OTW1, and OTW2 pins are active-low, open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other system-control device.

Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 go low when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature exceeds 100°C (see Table 1).

Note that asserting either RESET low forces the SD signal high, independent of faults being present. TI recommends monitoring the OTW signal using the system microcontroller and responding to an overtemperature warning signal by, for example, turning down the volume to prevent further heating of the device resulting in device shutdown (OTE).

To reduce external component count, an internal pullup resistor to 3.3 V is provided on both SD and OTW outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see Electrical Characteristics for further specifications).

7.3.4 Device Protection System

The TAS5630B contains advanced protection circuitry carefully designed to facilitate system integration and ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as short circuits, overload, overtemperature, and undervoltage. The TAS5630B responds to a fault by immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been removed, that is, the supply voltage has increased.

The device functions on errors, as shown in the following table.

Bootstrap UVP does not shut down according to the table; it shuts down the respective half-bridge.

7.3.5 Pin-to-Pin Short-Circuit Protection (PPSC)

The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent after the demodulation filter, whereas PPSC detects shorts directly at the pin before the filter. PPSC detection is performed at startup, that is, when VDD is supplied; consequently, a short to either GND_X or PVDD_X after system startup does not activate the PPSC detection system. When PPSC detection is activated by a short on the output, all half-bridges are kept in a Hi-Z state until the short is removed; the device then continues the startup sequence and starts switching. The detection is controlled globally by a two-step sequence. The first step ensures that there are no shorts from OUT_X to GND_X; the second step tests that there are no shorts from OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The typical duration is <15 ms/μF. While the PPSC detection is in progress, SD is kept low, and the device does not react to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and SD is released, a device reset does not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output configurations; the detection is not performed in SE mode. To make sure the PPSC detection system is not tripped, it is recommended not to insert resistive load between OUT_X and GND_X or PVDD_X.

7.3.6 Overtemperature Protection

The two different package options have individual overtemperature protection schemes.

PHD Package:
The TAS5630B PHD package option has a three-level temperature-protection system that asserts an active-low warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation. For highest reliability, the RESET should not be asserted until OTW1 has cleared.

DKD Package:
The TAS5630B DKD package option has a two-level temperature-protection system that asserts an active-low warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted. It is recommended to wait until OTW has cleared before asserting RESET. Thereafter, the device resumes normal operation.

7.3.7 Undervoltage Protection (UVP) and Power-On Reset (POR)

The UVP and POR circuits of the TAS5630B fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully operational when the GVDD_X and VDD supply voltages reach the levels stated in Electrical Characteristics. Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and SD being asserted low. The device automatically resumes operation when all supply voltages have increased above the UVP threshold.

7.3.8 Device Reset

When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance (Hi-Z) state.

In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high-impedance state when asserting the reset input low. Asserting reset input low removes any fault information to be signaled on the SD output; that is, SD is forced high. A rising-edge transition on reset input allows the device to resume operation after an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of SD.

7.3.9 Click and Pop in SE-Mode

The BTL startup has low click and pop due to the trimmed output dc offset, see Audio Characteristics (BTL).

The startup of the BTL+2 x SE system (Figure 21) or 4xSE (Figure 20) is more difficult to get click and pop free, than the pure BTL solution; therefore, evaluating the resulting click and pop before designing in the device is recommended.

7.3.10 PBTL Overload and Short Circuit

The TAS5630B has extensive overload and short circuit protection. In BTL and SE mode, it is fully protected against speaker terminal overloads, terminal-to-terminal short circuit, and short circuit to GND or PVDD. The protection works by limiting the current, by flipping the state of the output MOSFETs; thereby, ramping currents down in the inductor. This only works when the inductor is NOT saturated, the recommended minimum inductor values are listed in Recommended Operating Conditions. In BTL mode, the short circuit currents can reach more than 15 A, so when connecting the device in PBTL mode (Mono), the currents double – that is more than 30 A, and with these high currents, the protection system will limit PBTL speaker overloads, terminal-to-terminal shorts, and terminal-to-GND shorts. PBTL mode short circuit to PVDD is not recommended.

7.3.11 Oscillator

The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin.

To reduce interference problems while using a radio receiver tuned within the AM band, the switching frequency can be changed from nominal to lower values. These values should be chosen such that the nominal and the lower-value switching frequencies together result in the fewest cases of interference throughout the AM band, and can be selected by the value of the FREQ_ADJ resistor connected to AGND in master mode.

For slave-mode operation, turn off the oscillator by pulling the FREQ_ADJ pin to VREG. This configures the OSC_I/O pins as inputs, which must be slaved from an external clock.

Table 3. Mode Selection Pins