JAJSE39 October   2017 TAS5634

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Audio Specification Stereo (BTL)
    6. 7.6 Audio Specifications Mono (PBTL)
    7. 7.7 Audio Specification 4 Channels (SE)
    8. 7.8 Electrical Characteristics
    9. 7.9 Typical Characteristics
      1. 7.9.1 BTL Configuration
      2. 7.9.2 PBTL Configuration
      3. 7.9.3 SE Configuration
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Closed-Loop Architecture
      2. 8.3.2  Power Supplies
        1. 8.3.2.1 BST, Bootstrap Supply
        2. 8.3.2.2 PVDD, Output Stage Power Supply
        3. 8.3.2.3 GVDD, Gate-Drive Power Supply
        4. 8.3.2.4 VDD Supply, Internal Regulators (DVDD and AVDD)
      3. 8.3.3  System Power-Up / Power-Down Sequence
        1. 8.3.3.1 Powering Up
        2. 8.3.3.2 Powering Down
      4. 8.3.4  Startup and Shutdown Ramp Sequence (C_START)
      5. 8.3.5  Device Protection System
      6. 8.3.6  Overload and Short Circuit Current Protection
      7. 8.3.7  DC Speaker Protection
      8. 8.3.8  Pin-To-Pin Short Circuit Protection (PPSC)
      9. 8.3.9  Overtemperature Protection
      10. 8.3.10 Overtemperature Warning, OTW
      11. 8.3.11 Undervoltage Protection (UVP) and Power-On Reset (POR)
      12. 8.3.12 Error Reporting
      13. 8.3.13 Fault Handling
      14. 8.3.14 System Design Consideration
    4. 8.4 Device Functional Modes
      1. 8.4.1 Stereo, Bridge-tied Load (BTL)
      2. 8.4.2 Mono, Paralleled Bridge-tied Load (PBTL)
      3. 8.4.3 4-Channel, Single-ended (SE)
      4. 8.4.4 BD Modulation
      5. 8.4.5 Device Reset
      6. 8.4.6 Unused Output Channels
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical BTL Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Pin Connections
        4. 9.2.1.4 Application Curves
      2. 9.2.2 Typical PBTL Configuration
        1. 9.2.2.1 Application Curves
      3. 9.2.3 Typical SE Configuration
        1. 9.2.3.1 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supplies
    2. 10.2 Bootstrap Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material Recommendation
      2. 11.1.2 PVDD Capacitor Recommendation
      3. 11.1.3 Decoupling Capacitor Recommendation
      4. 11.1.4 Circuit Component Requirements
      5. 11.1.5 Printed Circuit Board Requirements
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

The TAS5634 is available in a thermally-enhanced, 44-Pin HTSSOP package (DDV).

The package contains a PowerPAD™ that is located on the top side of the device for convenient thermal coupling to a heatsink.

DDV Package
44 Pin (HTSSOP)
Top View

Pin Functions

PIN I/O/P(1) DESCRIPTION Sections
NAME NO.
AVDD 13 P Analog internal voltage regulator output. Place 1 μF capacitor to GND.
BST_A 44 P Bootstrap pin, A-side. Connect 0.33 nF ceramic capacitor to OUT_A.
BST_B 43 P Bootstrap pin, B-side. Connect 0.33 nF ceramic capacitor to OUT_B.
BST_C 24 P Bootstrap pin, C-side. Connect 0.33 nF ceramic capacitor to OUT_C.
BST_D 23 P Bootstrap pin, D-side. Connect 0.33 nF ceramic capacitor to OUT_D.
CLIP 18 O Clipping warning; open drain; active low. Connect 10 kΩ pull-up resistor to DVDD to monitor. If unused, do not connect.
C_START 7 O Startup ramp timing control pin. Connect capacitor to ground. 330nF for BTL / PBTL mode. 1 μF for SE mode.
DVDD 8 P Digital internal voltage regulator output. Place 1 μF capacitor to GND.
FAULT 16 O Fault signal output, open drain; active low. Connect 10 kΩ pull-up resistor to DVDD to monitor. If unused, do not connect.
GND 9, 10, 11, 12, 25, 26, 33, 34, 41, 42 P Ground.
GVDD_AB 1 P Gate-drive voltage supply; AB-side. Place 100 nF decoupling capacitor to GND.
GVDD_CD 22 P Gate-drive voltage supply; CD-side. Place 100 nF decoupling capacitor to GND.
INPUT_A 5 I PWM Input signal for half-bridge A. If unused, connect INPUT_A to GND.
INPUT_B 6 I PWM Input signal for half-bridge B. If unused, connect INPUT_B to GND.
INPUT_C 14 I PWM Input signal for half-bridge C. If unused, connect INPUT_C to GND.
INPUT_D 15 I PWM Input signal for half-bridge D. If unused, connect INPUT_D to GND.
M1 19 I Mode selection 1.
M2 20 I Mode selection 2.
M3 21 I Mode selection 3.
OC_ADJ 3 O Over-Current threshold programming pin. Connect programming resistor to GND. Use 27 kΩ for typical applications.
OTW 17 O Over-temperature warning; open drain; active low. Connect 10 kΩ pull-up resistor to DVDD to monitor. If unused, do not connect.
OUT_A 39, 40 O Output, half-bridge A. If unused, remove BST_A capacitor and GND INPUT_A pin. Output pins can be left floating.
OUT_B 35 O Output, half-bridge B. If unused, remove BST_B capacitor and GND INPUT_B pin. Output pins can be left floating.
OUT_C 32 O Output, half-bridge C. If unused, remove BST_C capacitor and GND INPUT_C pin. Output pins can be left floating.
OUT_D 27, 28 O Output, half-bridge D. If unused, remove BST_D capacitor and GND INPUT_D pin. Output pins can be left floating.
PVDD_AB 36, 37, 38 P PVDD supply for half-bridge A and B. Place a minimum of 1 μF decoupling capacitor near PVDD_AB pin.
PVDD_CD 29, 30, 31 P PVDD supply for half-bridge C and D. Place a minimum of 1 μF decoupling capacitor near PVDD_CD pin.
RESET 4 I Device reset pin; active low.
VDD 2 P 12V power supply input for internal analog and digital voltage regulators.
PowerPAD™ P Ground, connect to grounded heat sink.
(1) I = Input, O = Output, P = Power

Table 1. Mode Selection Pins

MODE PINS PWM Input(1) Output Configuration Input A Input B Input C Input D DC Speaker Protection(2) Mode C_START Capacitor
M3 M2 M1
0 0 0 2N 2 x BTL PWMa PWMb PWMc PWMd Enabled AD 330 nF
0 0 1 1N(3) 2 x BTL PWMa Unused PWMc Unused Enabled AD 330 nF
0 1 0 2N 2 x BTL PWMa PWMb PWMc PWMd Disabled AD or BD 330 nF
0 1 1 2N/1N(3) 1 x BTL + 2 x SE(4) PWMa PWMb PWMc PWMd Enabled (BTL only) AD 1 μF
1 0 0 2N 1 x PBTL PWMa PWMb 0 0 Enabled AD 330 nF
1 0 0 1N(3) 1 x PBTL PWMa Unused 0 1 Enabled AD 330 nF
1 0 0 2N 1 x PBTL PWMa PWMb 1 0 Disabled AD or BD 330 nF
1 0 1 1N1 4 x SE(5) PWMa PWMb PWMc PWMd Disabled AD 1 μF
(1) The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.
(2) DC Speaker Protection is disabled in BD mode due to in phase inductor ripple current.
(3) Using 1N interface in BTL and PBTL mode results in increased DC offset on the output terminals.
(4) In [011] 1 x BTL + 2 x SE mode, Output A and B refers to the BTL channel, and Output C and D the SE channels
(5) The 4xSE mode can be used as 1 x BTL + 2 x SE configuration by feeding a 2N PWM signal to either INPUT_AB or INPUT_CD