JAJSE39 October   2017 TAS5634

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Audio Specification Stereo (BTL)
    6. 7.6 Audio Specifications Mono (PBTL)
    7. 7.7 Audio Specification 4 Channels (SE)
    8. 7.8 Electrical Characteristics
    9. 7.9 Typical Characteristics
      1. 7.9.1 BTL Configuration
      2. 7.9.2 PBTL Configuration
      3. 7.9.3 SE Configuration
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Closed-Loop Architecture
      2. 8.3.2  Power Supplies
        1. 8.3.2.1 BST, Bootstrap Supply
        2. 8.3.2.2 PVDD, Output Stage Power Supply
        3. 8.3.2.3 GVDD, Gate-Drive Power Supply
        4. 8.3.2.4 VDD Supply, Internal Regulators (DVDD and AVDD)
      3. 8.3.3  System Power-Up / Power-Down Sequence
        1. 8.3.3.1 Powering Up
        2. 8.3.3.2 Powering Down
      4. 8.3.4  Startup and Shutdown Ramp Sequence (C_START)
      5. 8.3.5  Device Protection System
      6. 8.3.6  Overload and Short Circuit Current Protection
      7. 8.3.7  DC Speaker Protection
      8. 8.3.8  Pin-To-Pin Short Circuit Protection (PPSC)
      9. 8.3.9  Overtemperature Protection
      10. 8.3.10 Overtemperature Warning, OTW
      11. 8.3.11 Undervoltage Protection (UVP) and Power-On Reset (POR)
      12. 8.3.12 Error Reporting
      13. 8.3.13 Fault Handling
      14. 8.3.14 System Design Consideration
    4. 8.4 Device Functional Modes
      1. 8.4.1 Stereo, Bridge-tied Load (BTL)
      2. 8.4.2 Mono, Paralleled Bridge-tied Load (PBTL)
      3. 8.4.3 4-Channel, Single-ended (SE)
      4. 8.4.4 BD Modulation
      5. 8.4.5 Device Reset
      6. 8.4.6 Unused Output Channels
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical BTL Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Pin Connections
        4. 9.2.1.4 Application Curves
      2. 9.2.2 Typical PBTL Configuration
        1. 9.2.2.1 Application Curves
      3. 9.2.3 Typical SE Configuration
        1. 9.2.3.1 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supplies
    2. 10.2 Bootstrap Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material Recommendation
      2. 11.1.2 PVDD Capacitor Recommendation
      3. 11.1.3 Decoupling Capacitor Recommendation
      4. 11.1.4 Circuit Component Requirements
      5. 11.1.5 Printed Circuit Board Requirements
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range unless otherwise noted (1)
MIN MAX UNIT
VDD to GND, GVDD_X(3) to GND –0.3 13.2 V
PVDD_X(3) to GND –0.3 65 V
PVDD_X(3) to GND(2) (Less than 8ns transient) -0.3 71 V
OUT_X to GND -0.3 65 V
OUT_X to GND(2) (Less than 8ns transient) -7 71 V
BST_X to OUT_X(3) –0.3 13.2 V
DVDD to GND –0.3 4.2 V
AVDD to GND –0.3 8.5 V
OC_ADJ, M1, M2, M3, C_START, INPUT_X to GND –0.3 4.2 V
RESET, FAULT, OTW, CLIP, to GND –0.3 4.2 V
Maximum continuous sink current (FAULT, OTW, CLIP) 9 mA
Maximum operating junction temperature range, TJ 0 150 °C
Storage temperature, Tstg –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
(3) GVDD_X and PVDD_X represents a full bridge gate drive or power supply. GVDD_X is GVDD_AB or GVDD_CD, PVDD_X is PVDD_AB or PVDD_CD

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) (3) ±2000 V
Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) (3) ±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) Maximum BST_X to GND voltage is the sum of maximum PVDD to GND and GVDD to GND voltages minus a diode drop.

7.3 Recommended Operating Conditions

MIN TYP MAX UNIT
PVDD_X Full-bridge supply DC supply voltage 12 58 62 V
GVDD_X Supply for logic regulators and gate-drive circuitry DC supply voltage 10.8 12 13.2 V
VDD Digital regulator supply voltage DC supply voltage 10.8 12 13.2 V
RL Load impedance BTL Output filter: L = 15 uH, 0.68 µF 5 8 Ω
PBTL 3 4
SE 3 4
LOUTPUT Output filter inductance Minimum inductance at overcurrent limit, including inductor tolerance, temperature and possible inductor saturation 7 15 μH
fPWM PWM frame rate 352 384 500 kHz
CPVDD PVDD close decoupling capacitors 0.44 1 μF
C_START Startup ramp capacitor BTL and PBTL configuration 330 nF
SE and 1xBTL + 2xSE configuration 1 μF
ROC Over-current programming resistor, Resistor tolerance = 5% 24 27 33 kΩ
ROC_LATCHED Over-current programming resistor, Resistor tolerance = 5% 47 56 62 kΩ
TJ Junction temperature 0 125 °C

7.4 Thermal Information

THERMAL METRIC(1) TAS5634 UNIT
DDV (HTSSOP)
44 PINS
RθJA Junction-to-ambient thermal resistance 2.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.4 °C/W
RθJB Junction-to-board thermal resistance 2.0 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 1.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Audio Specification Stereo (BTL)

Audio performance is recorded as a chipset consisting of a TAS5548 PWM Processor (AD-mode, modulation index limited to 97.7%) and a TAS5634 power stage with PCB and system configurations in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 58 V, GVDD_X = 12 V, RL = 6 Ω, fS = 384 kHz, ROC = 30 kΩ, TC = 75°C, Output Filter: LDEM = 15 μH, CDEM = 680 nF, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PO Power output per channel RL = 8 Ω, 10% THD+N 230 W
RL = 6 Ω, 10% THD+N Tc = 25°C 300
RL = 6 Ω, 10% THD+N 295
RL = 8 Ω, 1% THD+N 180
RL = 6 Ω, 1% THD+N 240
THD+N Total harmonic distortion + noise 1 W, 1 kHz signal 0.025 %
Vn Output integrated noise A-weighted, AES17 measuring filter, dither off, noise shaper off(1) 215 μV
VOS Output offset voltage No signal 50 mV
SNR Signal-to-noise ratio(2) A-weighted, AES17 measuring filter, noise shaper off 105 dB
DNR Dynamic range A-weighted, –60 dBFS (rel 1% THD+N), noise shaper on 102 dB
Pidle Power dissipation due to Idle losses (IPVDD_X) PO = 0, channels switching(3) 8.6 W
(1) It is recommended to turn off PWM processor noise shaper while no audio present for lowest output noise
(2) SNR is calculated relative to 1% THD-N output level.
(3) Actual system idle losses also are affected by core losses of output inductors.

7.6 Audio Specifications Mono (PBTL)

Audio performance is recorded as a chipset consisting of a TAS5548 PWM Processor (AD-mode, modulation index limited to 97.7%) and a TAS5634 power stage with PCB and system configurations in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 58 V, GVDD_X = 12 V, RL = 3 Ω, fS = 384 kHz, ROC = 30 kΩ, TC = 75°C, Output Filter: LDEM = 15 μH, CDEM = 680 nF, CDCB = 470 µF, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PO Power output per channel RL = 4 Ω, 10% THD+N 460 W
RL = 3 Ω, 10% THD+N 590
RL = 3 Ω, 10% THD+N, PVDD = 58.5V 600
RL = 4 Ω, 1% THD+N 365
RL = 3 Ω, 1% THD+N 465
THD+N Total harmonic distortion + noise 1 W, 1 kHz signal 0.04 %
Vn Output integrated noise A-weighted, AES17 measuring filter, dither off, noise shaper off (1) 214 μV
VOS Output offset voltage No signal 50 mV
SNR Signal-to-noise ratio(2) A-weighted, AES17 measuring filter, noise shaper off 105 dB
DNR Dynamic range A-weighted, -60dBFS (rel 1% THD+N), noise shaper on 102 dB
Pidle Power dissipation due to Idle losses (IPVDD_X) PO = 0, channels switching(3) 8.6 W
(1) It is recommended to turn off PWM processor noise shaper while no audio present for lowest output noise
(2) SNR is calculated relative to 1% THD-N output level.
(3) Actual system idle losses also are affected by core losses of output inductors.

7.7 Audio Specification 4 Channels (SE)

Audio performance is recorded as a chipset consisting of a TAS5548 PWM Processor (AD-mode, modulation index limited to 97.7%) and a TAS5634 power stage with PCB and system configurations in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 58 V, GVDD_X = 12 V, RL = 3 Ω, fS = 384 kHz, ROC = 30 kΩ, TC = 75°C, Output Filter: LDEM = 15 μH, CDEM = 680 nF, CDCB = 470 µF, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PO Power output per channel RL = 4 Ω, 10% THD+N 110 W
RL = 3 Ω, 10% THD+N Tc = 25°C 150
RL = 3 Ω, 10% THD+N 145
RL = 4 Ω, 1% THD+N 90
RL = 3 Ω, 1% THD+N 115
THD+N Total harmonic distortion + noise 1 W, 1 kHz signal 0.05 %
Vn Output integrated noise A-weighted, AES17 measuring filter, dither off, noise shaper off(1) 145 μV
SNR Signal-to-noise ratio(2) A-weighted, AES17 measuring filter, noise shaper off 102 dB
DNR Dynamic range A-weighted, –60 dBFS (rel 1% THD+N), noise shaper on 102 dB
Pidle Power dissipation due to Idle losses (IPVDD_X) PO = 0, channels switching(3) 8.6 W
(1) It is recommended to turn off PWM processor noise shaper while no audio present for lowest output noise
(2) SNR is calculated relative to 1% THD-N output level.
(3) Actual system idle losses also are affected by core losses of output inductors.

7.8 Electrical Characteristics

PVDD_X = 58 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
DVDD Voltage regulator, only used as a reference node VDD = 12 V 3.0 3.3 3.6 V
AVDD Voltage regulator, only used as a reference node VDD = 12 V 7.8 V
IVDD VDD supply current Operating, 50% duty cycle 23 mA
Idle, reset mode 23
IGVDD_X Gate-supply current per full-bridge 50% duty cycle 22 mA
Reset mode 3
IPVDD_X Full-bridge idle current 50% duty cycle without load 148 mA
RESET low 3.5
OUTPUT-STAGE MOSFETs
RDS(on), LS Drain-to-source resistance, low side (LS) TJ = 25°C, excludes metallization resistance,
GVDD = 12 V		 80 mΩ
RDS(on), HS Drain-to-source resistance, high side (HS) 80 mΩ
I/O PROTECTION
Vuvp,GVDD Undervoltage protection limit, GVDD_X 8.5 V
Vuvp,GVDD, hyst (1) 0.7 V
Vuvp,VDD Undervoltage protection limit, VDD 8.5 V
Vuvp,VDD, hyst (1) 0.7 V
Vuvp,PVDD Undervoltage protection limit, PVDD_X 8.5 V
Vuvp,PVDD,hyst (1) 0.7 V
OTW(1) Overtemperature warning 115 125 135 °C
OTWhyst (1) Temperature drop needed below OTW temperature for OTW to be inactive after OTW event. 20 °C
OTE(1) Overtemperature error 145 155 165 °C
OTE-OTWdifferential (1) OTE-OTW differential 30 °C
OTEHYST (1) A device reset is needed to clear FAULT after an OTE event 20 °C
OLPC Overload protection counter fPWM = 384 kHz 2.6 ms
IOC Overcurrent limit protection Resistor – programmable, nominal peak current in 1Ω load, ROC = 27 kΩ (Typ) 14 A
IOC_LATCHED Overcurrent limit protection, latched Resistor – programmable, nominal peak current in 1Ω load, ROC = 56 kΩ (Typ) 14 A
IDC_OC Speaker DC protection limit Resistor – programmable, ROC = 27 kΩ 1.5 A
IDC_OC_LATCHED Speaker DC protection limit Resistor – programmable, ROC = 56 kΩ 1.5 A
IOCT Overcurrent response time Time from application of short condition to Hi-Z of affected half bridge 150 ns
IPD Internal pulldown resistor at output of each half bridge Connected when RESET is active to provide bootstrap charge. Not used in SE mode. 3 mA
STATIC DIGITAL SPECIFICATIONS
VIH High level input voltage INPUT_X, M1, M2, M3, RESET 1.9 V
VIL Low level input voltage 0.8 V
LEAKAGE Input leakage current 100 μA
OTW / SHUTDOWN (FAULT)
RINT_PU Internal pullup resistance, OTW, CLIP, FAULT to DVDD 20 26 33 kΩ
VOH High level output voltage Internal pullup resistor 3 3.3 3.6 V
VOL Low level output voltage IO = 4mA 200 500 mV
FANOUT Device fanout OTW, FAULT, CLIP No external pullup 30 devices
(1) Specified by design.

7.9 Typical Characteristics

7.9.1 BTL Configuration

Measurement Conditions: TAS5548 PWM Processor (AD-mode, modulation index limited to 97.7%), Audio frequency = 1 kHz, PVDD_X = 58 V, GVDD_X = 12 V, RL = 6 Ω, fS = 384 kHz, ROC = 30 kΩ, TC = 75°C, Output Filter: LDEM = 15 μH, CDEM = 680 nF, 20 Hz to 20 kHz BW (AES17 low pass filter), unless otherwise noted.

TAS5634 D001_SLAS931.gif
Figure 1. Total Harmonic Distortion + Noise vs Output Power
TAS5634 D002_SLAS931.gif
Figure 3. Total Harmonic Distortion + Noise vs Frequency
TAS5634 D003_SLAS931.gif
Figure 2. Output Power vs Supply Voltage
TAS5634 D004_SLAS931.gif
Figure 4. Output Power vs Supply Voltage
TAS5634 D005_SLAS931_option1.gif
Figure 5. Efficiency vs 2 Channel Output Power
TAS5634 D007_SLAS931.gif
Figure 7. Output Power vs Case Temperature
TAS5634 D006_SLAS931.gif
Figure 6. Power Loss vs 2 Channel Output Power
TAS5634 D008_SLAS931.gif
Figure 8. Noise Amplitude vs Frequency

7.9.2 PBTL Configuration

Measurement Conditions: TAS5548 PWM Processor (AD-mode, modulation index limited to 97.7%), Audio frequency = 1 kHz, PVDD_X = 58 V, GVDD_X = 12 V, RL = 3 Ω, fS = 384 kHz, ROC = 30 kΩ, TC = 75°C, Output Filter: LDEM = 15 μH, CDEM = 680 nF, CDCB = 470 µF, 20 Hz to 20 kHz BW (AES17 low pass filter), unless otherwise noted.

TAS5634 D014_SLAS931.gif
Figure 9. Total Harmonic Distortion + Noise vs Output Power
TAS5634 D015_SLAS931.gif
Figure 11. Total Harmonic Distortion + Noise vs Frequency
TAS5634 D018_SLAS931.gif
Figure 13. Output Power vs Case Temperature
TAS5634 D016_SLAS931.gif
Figure 10. Output Power vs Supply Voltage
TAS5634 D017_SLAS931.gif
Figure 12. Output Power vs Supply Voltage

7.9.3 SE Configuration

Measurement Conditions: TAS5548 PWM Processor (AD-mode, modulation index limited to 97.7%), Audio frequency = 1 kHz, PVDD_X = 58 V, GVDD_X = 12 V, RL = 3 Ω, fS = 384 kHz, ROC = 30 kΩ, TC = 75°C, Output Filter: LDEM = 15 μH, CDEM = 680 nF, CDCB = 470 µF, 20 Hz to 20 kHz BW (AES17 low pass filter), unless otherwise noted.

TAS5634 D009_SLAS931.gif
1.
Figure 14. Total Harmonic Distortion + Noise vs Output Power
TAS5634 D010_SLAS931.gif
Figure 16. Total Harmonic Distortion + Noise vs Frequency
TAS5634 D013_SLAS931.gif
Figure 18. Output Power vs Case Temperature
TAS5634 D011_SLAS931.gif
1.
Figure 15. Output Power vs Supply Voltage
TAS5634 D012_SLAS931.gif
Figure 17. Output Power vs Supply Voltage