SLOS838C July   2013  – August 2015 TAS5731M

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  PWM Operation at Recommended Operating Conditions
    6. 7.6  DC Electrical Characteristics
    7. 7.7  AC Electrical Characteristics (BTL, PBTL)
    8. 7.8  Electrical Characteristics - PLL External Filter Components
    9. 7.9  Electrical Characteristic - I2C Serial Control Port Operation
    10. 7.10 Timing Requirements - PLL Input Parameters
    11. 7.11 Timing Requirements - Serial Audio Ports Slave Mode
    12. 7.12 Timing Requirements - I2C Serial Control Port Operation
    13. 7.13 Timing Requirements - Reset (RESET)
    14. 7.14 Typical Characteristics
      1. 7.14.1 Typical Characteristics, 2.1 SE Configuration, 4 Ω
      2. 7.14.2 Typical Characteristics, 2.0 BTL Configuration, 8 Ω
      3. 7.14.3 Typical Characteristics, PBTL Configuration, 8 Ω
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1  Power Supply
      2. 9.3.2  I2C Address Selection and Fault Output
      3. 9.3.3  Single-Filter PBTL Mode
      4. 9.3.4  Device Protection System
        1. 9.3.4.1 Overcurrent (OC) Protection With Current Limiting
        2. 9.3.4.2 Overtemperature Protection
        3. 9.3.4.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
      5. 9.3.5  SSTIMER Functionality
      6. 9.3.6  Clock, Autodetection, and PLL
      7. 9.3.7  PWM Section
      8. 9.3.8  2.1-Mode Support
      9. 9.3.9  I2C Compatible Serial Control Interface
      10. 9.3.10 Audio Serial Interface
        1. 9.3.10.1 I2S Timing
        2. 9.3.10.2 Left-Justified
        3. 9.3.10.3 Right-Justified
      11. 9.3.11 Dynamic Range Control (DRC)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Stereo BTL Mode
      2. 9.4.2 Mono PBTL Mode
      3. 9.4.3 2.1 Mode
    5. 9.5 Programming
      1. 9.5.1 I2C Serial Control Interface
        1. 9.5.1.1 General I2C Operation
        2. 9.5.1.2 Single- and Multiple-Byte Transfers
        3. 9.5.1.3 Single-Byte Write
        4. 9.5.1.4 Multiple-Byte Write
        5. 9.5.1.5 Single-Byte Read
        6. 9.5.1.6 Multiple-Byte Read
      2. 9.5.2 26-Bit 3.23 Number Format
    6. 9.6 Register Maps
      1. 9.6.1  Clock Control Register (0x00)
      2. 9.6.2  Device ID Register (0x01)
      3. 9.6.3  Error Status Register (0x02)
      4. 9.6.4  System Control Register 1 (0x03)
      5. 9.6.5  Serial Data Interface Register (0x04)
      6. 9.6.6  System Control Register 2 (0x05)
      7. 9.6.7  Soft Mute Register (0x06)
      8. 9.6.8  Volume Registers (0x07, 0x08, 0x09, 0x0A)
      9. 9.6.9  Volume Configuration Register (0x0E)
      10. 9.6.10 Modulation Limit Register (0x10)
      11. 9.6.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
      12. 9.6.12 PWM Shutdown Group Register (0x19)
      13. 9.6.13 Start/Stop Period Register (0x1A)
      14. 9.6.14 Oscillator Trim Register (0x1B)
      15. 9.6.15 BKND_ERR Register (0x1C)
      16. 9.6.16 Input Multiplexer Register (0x20)
      17. 9.6.17 Channel 4 Source Select Register (0x21)
      18. 9.6.18 PWM Output Mux Register (0x25)
      19. 9.6.19 DRC Control Register (0x46)
      20. 9.6.20 Bank Switch and EQ Control Register (0x50)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo Bridge Tied Load Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Component Selection and Hardware Connections
          2. 10.2.1.2.2 I2C Pullup Resistors
          3. 10.2.1.2.3 Digital I/O Connectivity
          4. 10.2.1.2.4 Recommended Start-Up and Shutdown Procedures
            1. 10.2.1.2.4.1 Initialization Sequence
            2. 10.2.1.2.4.2 Normal Operation
            3. 10.2.1.2.4.3 Shutdown Sequence
            4. 10.2.1.2.4.4 Power-Down Sequence
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Mono Parallel Bridge Tied Load Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 2.1 Application
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 DVDD and AVDD Supplies
    2. 11.2 PVDD Power Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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発注情報

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

Figure 68, Figure 71, and Figure 72 highlight the required external components and system level connections for proper operation of the device in several popular use cases.

Each of these configurations can be realized using the Evaluation Modules (EVMs) for the device. These flexible modules allow full evaluation of the device in the most common modes of operation. Any design variation can be supported by TI through schematic and layout reviews. Visit http://e2e.ti.com for design assistance and join the audio amplifier discussion forum for additional information.

10.2 Typical Applications

10.2.1 Stereo Bridge Tied Load Application

A stereo system generally refers to a system in which there are two full range speakers without a separate amplifier path for the speakers that reproduce the low-frequency content. In this system, two channels are presented to the amplifier via the digital input signal. These two channels are amplified and then sent to two separate speakers.

Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the audio for the left channel and the other channel containing the audio for the right channel.

The Stereo BTL Configuration with Headphone and Line Driver Amplifier application is shown in Figure 68.

TAS5731M Stereo_BTL_Mode.gifFigure 68. Stereo Bridge Tied Load Application

10.2.1.1 Design Requirements

SPACE

Table 24. Design Requirements

PARAMETER EXAMPLE
Low Power Supply 3.3 V
High Power Supply 8 V to 24 V
Host Processor I2S Compliant Master
I2C Compliant Master
GPIO Control
Output Filters Inductor-Capacitor Low Pass Filter
Speaker 4 Ω minimum

10.2.1.2 Detailed Design Procedure

10.2.1.2.1 Component Selection and Hardware Connections

The typical connections required for proper operation of the device can be found in the TAS5731EVM User’s Guide (SLOU331). The device was tested with this list of components; deviation from this list of typical application components, unless recommended by this document, may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device.

10.2.1.2.2 I2C Pullup Resistors

Customary pullup resistors are required on the SCL and SDA signal lines. They are not shown in the Typical Application Circuits, because they are shared by all of the devices on the I2C bus and are considered to be part of the associated passive components for the System Processor. These resistor values must be chosen per the guidance provided in the I2C Specification.

10.2.1.2.3 Digital I/O Connectivity

The digital I/O lines of the TAS5731M are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it must be connected to DVDD through a pullup resistor to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count.

10.2.1.2.4 Recommended Start-Up and Shutdown Procedures

TAS5731M T0419-06_LOS838.gifFigure 69. Recommended Command Sequence
TAS5731M T0420-05_LOS645.gifFigure 70. Power-Loss Sequence

10.2.1.2.4.1 Initialization Sequence

Use the following sequence to power up and initialize the device:
1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3 V.
2. Initialize digital inputs and PVDD supply as follows:
Drive RESET = 0, PDN = 1, and other digital inputs to their desired state while ensuring that all are never more than 2.5 V above AVDD/DVDD. Wait at least 100 µs, drive RESET = 1, and wait at least another 13.5 ms.
Ramp up PVDD to at least 8 V while ensuring that it remains below 6 V for at least 100 µs after AVDD/DVDD reaches 3 V. Then wait at least another 10 µs.
3. Trim oscillator (write 0x00 to register 0x1B) and wait at least 50 ms.
4. Configure the DAP via I2C, see TAS5731EVM Evaluation Module User's Guide (SLOU331) for typical values.
5. Configure remaining registers.
6. Exit shutdown (sequence defined inShutdown Sequence).

10.2.1.2.4.2 Normal Operation

The following are the only events supported during normal operation:
1. Writes to master/channel volume registers
2. Writes to soft-mute register
3. Enter and exit shutdown (sequence defined in Shutdown Sequence)

NOTE

Event 3 is not supported for 240 ms + 1.3 × tstart after trim following AVDD/DVDD power-up ramp (where tstart is specified by register 0x1A).

10.2.1.2.4.3 Shutdown Sequence

Enter:
1. Write 0x40 to register 0x05.
2. Wait at least 1 ms + 1.3 × tstop (where tstop is specified by register 0x1A).
3. If desired, reconfigure by returning to step 4 of initialization sequence.
Exit:
1. Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240 ms after trim following AVDD/DVDD power-up ramp).
2. Wait at least 1 ms + 1.3 × tstart (where tstart is specified by register 0x1A).
3. Proceed with normal operation.

10.2.1.2.4.4 Power-Down Sequence

Use the following sequence to power down the device and its supplies:
1. If time permits, enter shutdown (sequence defined in Shutdown Sequence); else, in case of sudden power loss, assert PDN = 0 and wait at least 2 ms.
2. Assert RESET = 0.
3. Drive digital inputs low and ramp down PVDD supply as follows:
Drive all digital inputs low after RESET has been low for at least 2 µs.
Ramp down PVDD while ensuring that it remains above 8 V until RESET has been low for at least 2 µs.
4. Ramp down AVDD/DVDD while ensuring that it remains above 3 V until PVDD is below 6 V and that it is never more than 2.5 V below the digital inputs.

10.2.1.3 Application Curves

space

Table 25. Relevant Performance Curves

CURVE TITLE FIGURE
Output Power vs Supply Voltage (2.0 BTL Mode)
With 4ω Load on Typical 2 Layer PCB Device May Be Thermally Limited Above 20 V
Figure 18
Total Harmonic Distortion + Noise vs Output Power (2.0 BTL Mode) Figure 19
Total Harmonic Distortion + Noise vs Output Power (2.0 BTL Mode) Figure 20
Total Harmonic Distortion + Noise vs Output Power (2.0 BTL Mode) Figure 21
Total Harmonic Distortion vs Frequency (2.0 BTL Mode) Figure 22
Total Harmonic Distortion vs Frequency (2.0 BTL Mode) Figure 23
Total Harmonic Distortion vs Frequency (2.0 BTL Mode) Figure 24
Efficiency vs Output Power (2.0 BTL Mode) Figure 25
Crosstalk vs Frequency (2.0 BTL Mode) Figure 26
Crosstalk vs Frequency (2.0 BTL Mode) Figure 27
Crosstalk vs Frequency (2.0 BTL Mode) Figure 28
Crosstalk vs Frequency (2.0 BTL Mode) Figure 29
Power vs Supply Voltage (2.0 BTL Mode) Figure 30
Idle Channel Noise vs Supply Voltage (2.0 BTL Mode) Figure 31

10.2.2 Mono Parallel Bridge Tied Load Application

A mono system refers to a system in which the amplifier is used to drive a single loudspeaker. Parallel Bridge Tied Load (PBTL) indicates that the two full-bridge channels of the device are placed in parallel and drive the loudspeaker simultaneously using an identical audio signal. The primary benefit of operating the TAS5731M device in PBTL operation is to reduce the power dissipation and increase the current sourcing capabilities of the amplifier output. In this mode of operation, the current limit of the audio amplifier is approximately doubled while the on-resistance is approximately halved.

The loudspeaker can be a full-range transducer or one that only reproduces the low-frequency content of an audio signal, as in the case of a powered subwoofer. Often in this use case, two stereo signals are mixed together and sent through a low-pass filter in order to create a single audio signal which contains the low frequency information of the two channels.

The Mono Parallel Bridge Tied Load application is shown in Figure 71.

TAS5731M B0264-26_SLOS838.gifFigure 71. Mono Parallel Bridge Tied Load Application

10.2.2.1 Design Requirements

SPACE

Table 26. Design Requirements

PARAMETER EXAMPLE
Low Power Supply 3.3 V
High Power Supply 8 V to 24 V
Host Processor I2S Compliant Master
I2C Compliant Master
GPIO Control
Output Filters Inductor-Capacitor Low Pass Filter
Speaker 4 Ω minimum

10.2.2.2 Detailed Design Procedure

Refer to Detailed Design Procedure for information.

10.2.2.3 Application Curves

SPACE

Table 27. Relevant Performance Curves

CURVE TITLE FIGURE
Output Power vs Supply Voltage (PBTL Mode)
With 2ω Load on Typical 2 Layer PCB, Device May Be Thermally Limited Above 20 V
Figure 32
Total Harmonic Distortion + Noise vs Output Power (PBTL Mode) Figure 33
Total Harmonic Distortion + Noise vs Output Power (PBTL Mode) Figure 34
Total Harmonic Distortion + Noise vs Output Power (PBTL Mode) Figure 35
Total Harmonic Distortion vs Frequency (PBTL Mode) Figure 36
Total Harmonic Distortion vs Frequency (PBTL Mode) Figure 37
Total Harmonic Distortion vs Frequency (PBTL Mode) Figure 38
Efficiency vs Output Power (PBTL Mode) Figure 39
Efficiency vs Output Power (PBTL Mode) Figure 40
Power vs Supply Voltage (PBTL Mode) Figure 41
Idle Channel Noise vs Supply Voltage (PBTL Mode) Figure 42

10.2.3 2.1 Application

A 2.1 system generally refers to a system in which there are two full range speakers with a separate amplifier path for the speakers which reproduce the low-frequency content. In this system, two channels are presented to the amplifier via the digital input signal, these are driven into two single-ended speakers and are mixed into a third channel, conditioned to stream low-frequency content into a differentially connected speaker.

The 2.1 application is shown in Figure 72.

TAS5731M B0264-25_SLOS838.gifFigure 72. Simplified 2.1 Application Diagram

10.2.3.1 Design Requirements

SPACE

Table 28. Design Requirements

PARAMETER EXAMPLE
Low Power Supply 3.3 V
High Power Supply 8 V to 24 V
Host Processor I2S Compliant Master
I2C Compliant Master
GPIO Control
Output Filters Inductor-Capacitor Low Pass Filter
Speaker 4 Ω (BTL), 2 Ω (SE) minimum

10.2.3.2 Detailed Design Procedure

Refer to Detailed Design Procedure for information.

10.2.3.3 Application Curves

SPACE

Table 29. Relevant Performance Curves

CURVE TITLE FIGURE
Output Power vs Supply Voltage (2.1 SE Mode)
With 2 × 4ω + 4ω Load on Typical 2 Layer PCB Device May Be Thermally Limited Above 20 V
Figure 5
Total Harmonic Distortion + Noise vs Output Power (2.1 SE Mode) Figure 6
Total Harmonic Distortion + Noise vs Output Power (2.1 SE Mode) Figure 7
Total Harmonic Distortion + Noise vs Output Power (2.1 SE Mode) Figure 8
Total Harmonic Distortion + Noise vs Frequency (2.1 SE Mode) Figure 9
Total Harmonic Distortion + Noise vs Frequency (2.1 SE Mode) Figure 10
Total Harmonic Distortion + Noise vs Frequency (2.1 SE Mode) Figure 11
Efficiency vs Total Output Power (2.1 SE Mode) Figure 12
Efficiency vs Total Output Power (2.1 SE Mode) Figure 13
Crosstalk vs Frequency (2.1 SE Mode) Figure 14
Crosstalk vs Frequency (2.1 SE Mode) Figure 15
Crosstalk vs Frequency (2.1 SE Mode) Figure 16
Crosstalk vs Frequency (2.1 SE Mode) Figure 17